Chip Pub Date : 2023-08-14 DOI: 10.1016/j.chip.2023.100061

Qiaolv Ling , Penghui Dong , Yayan Chu , Xiaowen Dong , Jingye Chen , Daoxin Dai , Yaocheng Shi

引用次数: 0

Van der Waals materials-based floating gate memory for neuromorphic computing 基于范德华材料的神经形态计算浮栅存储器

Chip Pub Date : 2023-07-20 DOI: 10.1016/j.chip.2023.100059

Qianyu Zhang , Zirui Zhang , Ce Li , Renjing Xu , Dongliang Yang , Linfeng Sun

{"title":"Van der Waals materials-based floating gate memory for neuromorphic computing","authors":"Qianyu Zhang , Zirui Zhang , Ce Li , Renjing Xu , Dongliang Yang , Linfeng Sun","doi":"10.1016/j.chip.2023.100059","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100059","url":null,"abstract":"<div><p>With the advent of the “Big Data Era”, improving data storage density and computation speed has become more and more urgent due to the rapid growth in different types of data. Flash memory with a floating gate (FG) structure is attracting great attention owing to its advantages of miniaturization, low power consumption and reliable data storage, which is very effective in solving the problems of large data capacity and high integration density. Meanwhile, the FG memory with charge storage principle can simulate synaptic plasticity perfectly, breaking the traditional von Neumann computing architecture and can be used as an artificial synapse for neuromorphic computations inspired by the human brain. Among many candidate materials for manufacturing devices, van der Waals (vdW) materials have attracted widespread attention due to their atomic thickness, high mobility, and sustainable miniaturization properties. Owing to the arbitrary stacking ability, vdW heterostructure combines rich physics and potential 3D integration, opening up various possibilities for new functional integrated devices with low power consumption and flexible applications. This paper provides a comprehensive review of memory devices based on vdW materials with FG structure, including the working principles and typical structures of FG structure devices, with a focus on the introduction of various high-performance FG memories and their versatile applications in neuromorphic computing. Finally, the challenges of neuromorphic devices based on FG structures are also discussed. This review will shed light on the design and fabrication of vdW material-based memory devices with FG engineering, helping to promote the development of practical and promising neuromorphic computing.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 4","pages":"Article 100059"},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71785366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Deep‐learning based on‐chip rapid spectral imaging with high spatial resolution 基于深度学习的高空间分辨率芯片快速光谱成像

Chip Pub Date : 2023-06-01 DOI: 10.1016/j.chip.2023.100045

Jiawei Yang , Kaiyu Cui , Yidong Huang , Wei Zhang , Xue Feng , Fang Liu

{"title":"Deep‐learning based on‐chip rapid spectral imaging with high spatial resolution","authors":"Jiawei Yang , Kaiyu Cui , Yidong Huang , Wei Zhang , Xue Feng , Fang Liu","doi":"10.1016/j.chip.2023.100045","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100045","url":null,"abstract":"<div><p>Spectral imaging extends the concept of traditional color cameras to capture images across multiple spectral channels and has broad application prospects. Conventional spectral cameras based on scanning methods suffer from the drawbacks of low acquisition speed and large volume. On-chip computational spectral imaging based on metasurface filters provides a promising scheme for portable applications, but endures long computation time due to point-by-point iterative spectral reconstruction and mosaic effect in the reconstructed spectral images. In this study, on-chip rapid spectral imaging was demonstrated, which eliminated the mosaic effect in the spectral image by deep-learning-based spectral data cube reconstruction. The experimental results show that 4 orders of magnitude faster than the iterative spectral reconstruction were achieved, and the fidelity of the spectral reconstruction for the standard color plate was over 99% for a standard color board. In particular, video-rate spectral imaging was demonstrated for moving objects and outdoor driving scenes with good performance for recognizing metamerism, where the concolorous sky and white cars can be distinguished via their spectra, showing great potential for autonomous driving and other practical applications in the field of intelligent perception.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100045"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

On-chip photonic spatial-temporal descrambler 片上光子时空解扰器

Chip Pub Date : 2023-06-01 DOI: 10.1016/j.chip.2023.100043

Wenkai Zhang , Xueyi Jiang , Wentao Gu , Junwei Cheng , Hailong Zhou , Jianji Dong , Dongmei Huang , Xinliang Zhang

{"title":"On-chip photonic spatial-temporal descrambler","authors":"Wenkai Zhang , Xueyi Jiang , Wentao Gu , Junwei Cheng , Hailong Zhou , Jianji Dong , Dongmei Huang , Xinliang Zhang","doi":"10.1016/j.chip.2023.100043","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100043","url":null,"abstract":"<div><p>As an indispensable part to compensate for the signal crosstalk in fiber communication systems, conventional digital multi-input multi-output (MIMO) signal processor is facing the challenges of high computational complexity, high power consumption and relatively low processing speed. The optical MIMOenables the best use of light and has been proposed to remedy this limitation. However, the currently existing optical MIMO methods are all restricted to the spatial dimension, while the temporal dimension is neglected. Here, an on-chip spatial-temporal descrambler with four channels were devised and its MIMO functions were experimentally verified simultaneously in both spatial and temporal dimensions. The spatial crosstalk of single-channel descrambler and four-channel descrambler is respectively less than -21 dB and -18 dB, and the time delay is simultaneously compensated successfully. Moreover, a more universal model extended to mode-dependent loss and gain (MDL) compensation was further developed, which is capable of being cascaded for the real optical transmission system. The first attempt at photonic spatial-temporal descrambler enriched the varieties of optical MIMO, and the proposed scheme provided a new opportunity for all-optical MIMO signal processing.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100043"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Electric-field-induced quasi-phase-matched three-wave mixing in silicon-based superlattice-on-insulator integrated circuits 绝缘体上硅基超晶格集成电路中电场诱导的准相位匹配三波混频

Chip Pub Date : 2023-06-01 DOI: 10.1016/j.chip.2023.100042

Richard Soref (Life Fellow IEEE) , Francesco De Leonardis

{"title":"Electric-field-induced quasi-phase-matched three-wave mixing in silicon-based superlattice-on-insulator integrated circuits","authors":"Richard Soref (Life Fellow IEEE) , Francesco De Leonardis","doi":"10.1016/j.chip.2023.100042","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100042","url":null,"abstract":"<div><p>We present a theoretical investigation, based on the tight-binding Hamiltonian, of efficient electric-field-induced three-waves mixing (EFIM) in an undoped lattice-matched short-period superlattice (SL) that integrates quasi-phase-matched (QPM) SL straight waveguides and SL racetrack resonators on an opto-electronic chip. Periodically reversed DC voltage is applied to electrode segments on each side of the strip waveguide. The spectra of <span><math><msubsup><mrow><mi>χ</mi></mrow><mrow><mi>xxxx</mi></mrow><mrow><mo>(</mo><mn>3</mn><mo>)</mo></mrow></msubsup></math></span> and of the linear susceptibility have been simulated as a function of the number of the atomic monolayers for “non-relaxed” heterointerfaces, and by considering all the transitions between valence and conduction bands. The large obtained values of<span><math><msubsup><mrow><mspace></mspace><mi>χ</mi></mrow><mrow><mi>xxxx</mi></mrow><mrow><mo>(</mo><mn>3</mn><mo>)</mo></mrow></msubsup></math></span> make the <span><math><mrow><msub><mrow><mo>(</mo><mi>ZnS</mi><mo>)</mo></mrow><mn>3</mn></msub><mo>/</mo><msub><mrow><mo>(</mo><mrow><mi>S</mi><msub><mi>i</mi><mn>2</mn></msub></mrow><mo>)</mo></mrow><mn>3</mn></msub></mrow></math></span> short-period SL a good candidate for realizing large effective second-order nonlinearity, enabling future high-performance of the SLOI PICs and OEICs in the 1000-nm and 2000-nm wavelengths ranges. We have made detailed calculations of the efficiency of second-harmonic generation and of the performances of the optical parametric oscillator (OPO). The results indicate that the <span><math><mrow><msub><mrow><mo>(</mo><mi>ZnS</mi><mo>)</mo></mrow><mi>N</mi></msub><mo>/</mo><msub><mrow><mo>(</mo><mrow><mi>S</mi><msub><mi>i</mi><mn>2</mn></msub></mrow><mo>)</mo></mrow><mi>M</mi></msub></mrow></math></span> QPM is competitive with present PPLN technologies and is practical for classical and quantum applications.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100042"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-loss beam synthesizing network based on Epsilon-near-zero (ENZ) medium for on-chip antenna array 基于Epsilon近零（ENZ）介质的片上天线阵列低损耗波束合成网络

Chip Pub Date : 2023-06-01 DOI: 10.1016/j.chip.2023.100049

Hao Li , Ziheng Zhou , Yongzhi Zhao , Yue Li

{"title":"Low-loss beam synthesizing network based on Epsilon-near-zero (ENZ) medium for on-chip antenna array","authors":"Hao Li , Ziheng Zhou , Yongzhi Zhao , Yue Li","doi":"10.1016/j.chip.2023.100049","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100049","url":null,"abstract":"<div><p>Beam synthesizing antenna arrays are essentially demanded for on-chip millimeter wave and terahertz systems. In order to achieve a particular radiation beam, specific amplitude and phase distributions are required for all the array elements, which is conventionally realized through a properly designed feeding network. In the current work, a low-loss feeding network design approach based on epsilon-near-zero (ENZ) medium was proposed for large-scale antenna arrays with different beam requirements. Due to the infinite wavelength within the ENZ medium, a newly-discovered stair-like resonant mode was adopted for assigning a uniform phase distribution to each element, while the amplitudes and positions of these elements were optimized for generating particular beams. To implement the design philosophy in a low-loss manner, a hollow air-filled waveguide near cutoff frequency was employed to emulate the ENZ medium, and the bulk silicon microelectromechanical systems (MEMS) micromachining technology was utilized for chip-scale integration. As a specific example, a low-sidelobe antenna array at 60.0 GHz was designed, which realized an impedance bandwidth of 2.57%, a gain of 13.6 dBi and a sidelobe level as low as -20.0 dB within the size of 0.5 × 3.4<em>λ</em><sub>0</sub><sup>2</sup>. This method is also compatible with a variety of applications, such as the high-directivity antenna array, non-diffractive Bessel beam antenna array, and so on. Based on this innovative concept of applying ENZ medium to the on-chip antenna array, it shows the advantages of simple structure and low loss for on-chip beam synthesis without complex lossy feeding networks.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100049"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Van der Waals ferroelectric transistors: the all-round artificial synapses for high-precision neuromorphic computing 范德华铁电晶体管：用于高精度神经形态计算的全方位人工突触

Chip Pub Date : 2023-06-01 DOI: 10.1016/j.chip.2023.100044

Zhongwang Wang , Xuefan Zhou , Xiaochi Liu , Aocheng Qiu , Caifang Gao , Yahua Yuan , Yumei Jing , Dou Zhang , Wenwu Li , Hang Luo , Junhao Chu , Jian Sun

{"title":"Van der Waals ferroelectric transistors: the all-round artificial synapses for high-precision neuromorphic computing","authors":"Zhongwang Wang , Xuefan Zhou , Xiaochi Liu , Aocheng Qiu , Caifang Gao , Yahua Yuan , Yumei Jing , Dou Zhang , Wenwu Li , Hang Luo , Junhao Chu , Jian Sun","doi":"10.1016/j.chip.2023.100044","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100044","url":null,"abstract":"<div><p><strong>State number, operation power, dynamic range and conductance weight update linearity are key synaptic device performance metrics for high-accuracy and low-power-consumption neuromorphic computing in hardware. However, high linearity and low power consumption couldn't be simultaneously achieved by most of the reported synaptic devices, which limits the performance of the hardware. This work demonstrates van der Waals (vdW) stacked ferroelectric field-effect transistors (FeFET) with single-crystalline ferroelectric nanoflakes. Ferroelectrics are of fine vdW interface and partial polarization switching of multi-domains under electric field pulses, which makes the FeFETs exhibit multi-state memory characteristics and excellent synaptic plasticity. They also exhibit a desired linear conductance weight update with 128 conductance states, a sufficiently high dynamic range of</strong> <em><strong>G</strong></em><sub><strong>max</strong></sub><strong>/</strong><em><strong>G</strong></em><sub><strong>min</strong></sub> <strong>> 120, and a low power consumption of 10 fJ/spike using identical pulses. Based on such an all-round device, a two-layer artificial neural network was built to conduct Modified National Institute of Standards and Technology (MNIST) digital numbers and electrocardiogram (ECG) pattern-recognition simulations, with the high accuracies reaching 97.6% and 92.4%, respectively. The remarkable performance demonstrates that vdW-FeFET is of obvious advantages in high-precision neuromorphic computing applications.</strong></p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100044"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ring-VCO-based phase-locked loops for clock generation – design considerations and state-of-the-art 用于时钟生成的基于环形VCO的锁相环——设计注意事项和最先进技术

Chip Pub Date : 2023-06-01 DOI: 10.1016/j.chip.2023.100051

Shiheng Yang , Jun Yin , Yueduo Liu , Zihao Zhu , Rongxin Bao , Jiahui Lin , Haoran Li , Qiang Li , Pui-In Mak , Rui P. Martins

引用次数: 0

Experimental investigation of measurement incompatibility of mutually unbiased bases 互无偏基测量不相容性的实验研究

Chip Pub Date : 2023-03-01 DOI: 10.1016/j.chip.2023.100041

Yu Guo , Shuming Cheng , Xiao-Min Hu , Bi-Heng Liu , Yun-Feng Huang , Chuan-Feng Li , Guang-Can Guo

引用次数: 1

Silicon-based decoder for polarization-encoding quantum key distribution 用于偏振编码量子密钥分配的硅基解码器

Chip Pub Date : 2023-03-01 DOI: 10.1016/j.chip.2023.100039

Yongqiang Du , Xun Zhu , Xin Hua , Zhengeng Zhao , Xiao Hu , Yi Qian , Xi Xiao , Kejin Wei

{"title":"Silicon-based decoder for polarization-encoding quantum key distribution","authors":"Yongqiang Du , Xun Zhu , Xin Hua , Zhengeng Zhao , Xiao Hu , Yi Qian , Xi Xiao , Kejin Wei","doi":"10.1016/j.chip.2023.100039","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100039","url":null,"abstract":"<div><p><strong>Silicon-based polarization-encoding quantum key distribution (QKD) has been extensively studied due to its advantageous characteristics of its low cost and robustness. However, given the difficulty of fabricating polarized independent components on the chip, previous studies have only adopted off-chip devices to demodulate the quantum states or perform polarization compensation. In the current work, a fully chip-based decoder for polarization-encoding QKD was proposed. The chip realized a polarization state analyzer and compensated for the BB84 protocol without the requirement of additional hardware, which was based on a polarization-to-path conversion method utilizing a polarization splitter-rotator. The chip was fabricated adopting a standard silicon photonics foundry, which was of a compact design and suitable for mass production. In the experimental stability test, an average quantum bit error rate of</strong> <span><math><mrow><mn>0.59</mn><mo>%</mo></mrow></math></span> <strong>was achieved through continuous operation for 10 h without any polarization feedback. Furthermore, the chip enabled the automatic compensation of the fiber polarization drift when utilizing the developed feedback algorithm, which was emulated by a random fiber polarization scrambler. Moreover, a finite-key secret rate of 240 bps over a fiber spool of 100 km was achieved in the case of the QKD demonstration. This study marks an important step toward the integrated, practical, and large-scale deployment of QKD systems.</strong></p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 1","pages":"Article 100039"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50183416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

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