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A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal 一种高速、低功耗、低电压的全差分CMOS采样保持电路
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465286
Tsung-Sum Lee, Chi-Chang Lu, S.H. Yu, J. Zhan
{"title":"A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal","authors":"Tsung-Sum Lee, Chi-Chang Lu, S.H. Yu, J. Zhan","doi":"10.1109/ISCAS.2005.1465286","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465286","url":null,"abstract":"A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully differential double-sampled design relaxes the trade-off between sampling speed and the sampling precision. Simulation results are given to demonstrate the potential advantage of the new technique.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"95 1","pages":"3111-3114"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78562353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 8-µW, 0.3-mm2 RF-powered transponder with temperature sensor for wireless environmental monitoring 一个8µW, 0.3 mm2射频功率应答器，带温度传感器，用于无线环境监测
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465697
Narrijun Cho, Seong-Jun Song, Jae-Youl Lee, Sunyoung Kim, Shiho Kim, H. Yoo
{"title":"A 8-µW, 0.3-mm2 RF-powered transponder with temperature sensor for wireless environmental monitoring","authors":"Narrijun Cho, Seong-Jun Song, Jae-Youl Lee, Sunyoung Kim, Shiho Kim, H. Yoo","doi":"10.1109/ISCAS.2005.1465697","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465697","url":null,"abstract":"We present an RF-powered transponder with temperature sensor for environmental monitoring. The transponder gathers power from the ISM (860-960 MHz) band RF signal. A temperature-compensated ring oscillator and an oversampling synchronizer are proposed for low power and robust system clock generation. The simple structure of the temperature sensor is achieved by sharing major reference signals with the ring oscillator. The generated clock frequency has a variation of less than 5% for 1-V supply voltage and 90/spl deg/C temperature changes. The temperature sensor has a resolution under 1/spl deg/C in the range from -10/spl deg/C to 80/spl deg/C. The transponder dissipates only 8-/spl mu/W during the active state and occupies 0.3 mm/sup 2/ with a 0.25-/spl mu/m CMOS process.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"776 1","pages":"4763-4766"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85440860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 78
A 60 ns 500×12 0.35µm CMOS low-power scanning read-out IC for cryogenic infra-red sensors 60 ns 500×12 0.35µm CMOS低功耗扫描读出IC用于低温红外传感器
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1464944
F. Serra-Graells, B. Misischi, E. Casanueva, C. Méndez, L. Terés
{"title":"A 60 ns 500×12 0.35µm CMOS low-power scanning read-out IC for cryogenic infra-red sensors","authors":"F. Serra-Graells, B. Misischi, E. Casanueva, C. Méndez, L. Terés","doi":"10.1109/ISCAS.2005.1464944","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1464944","url":null,"abstract":"The paper proposes a low-cost scanning read-out IC architecture for large arrays of infra-red photon sensors operating at cryogenic temperatures. The low-power and compact 50/spl times/100 /spl mu/m/sup 2/ active pixel sensor area is achieved by the use of novel CMOS basic building blocks for single-capacitor integration and correlated double sampling, embedded pixel-test, pixel charge-multiplexing, video multiplexing and offset calibration. As a result, a low-cost 500/spl times/12 and 60 ns/pixel system-on-chip realization, capable of capturing high-resolution and real-time infra-red images, such as 640/spl times/500 @ 100 fps or 2560/spl times/500 @ 25 fps, is presented for a standard 0.35 /spl mu/m CMOS technology.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"69 1","pages":"1742-1745"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74015261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Generalized alpha-VSH polynomials and stability of delta-operator based 2D discrete-time systems 广义vsh多项式与基于delta算子的二维离散系统的稳定性
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465111
H. Reddy, P. Rajan
{"title":"Generalized alpha-VSH polynomials and stability of delta-operator based 2D discrete-time systems","authors":"H. Reddy, P. Rajan","doi":"10.1109/ISCAS.2005.1465111","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465111","url":null,"abstract":"Delta (/spl delta/-) operator formulation for discrete time systems with sampling period T as explicit variable merges to the underlying continuous time system as T/spl rarr/0. The paper uses this fact in studying the stability of two-dimensional (2D) /spl delta/-discrete time (DT) systems and formulates the concept of the /spl alpha/-very strict Hurwitz polynomial (VSHP). This is related to the 2D (1//spl alpha/)-Schur polynomial through inverse variable transformation. The properties and test procedures for /spl alpha/-VSHF and its importance in the structural stability of 2D /spl delta/-DT systems are presented.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"118 1","pages":"2409-2412"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88038128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.35µm CMOS comparator circuit for high-speed ADC applications 用于高速ADC应用的0.35µm CMOS比较电路
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1466040
S. Sheikhaei, S. Mirabbasi, André Ivanov
{"title":"A 0.35µm CMOS comparator circuit for high-speed ADC applications","authors":"S. Sheikhaei, S. Mirabbasi, André Ivanov","doi":"10.1109/ISCAS.2005.1466040","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1466040","url":null,"abstract":"A high-speed differential clocked comparator circuit is presented. The comparator consists of a preamplifier and a latch stage followed by a dynamic latch that operates as an output sampler. The output sampler circuit consists of a full transmission gate (TG) and two inverters. The use of this sampling stage results in a reduction in the power consumption of this high-speed comparator. Simulations show that charge injection of the TG adds constructively to the sampled signal value, therefore amplifying the sampled signal with a modest gain of 1.15. Combined with the high gain of the inverters, the sampled signals are amplified toward the rail voltages. This comparator is designed and fabricated in a 0.35 /spl mu/m standard digital CMOS technology. Measurement results show a sampling frequency of 1 GHz with 16 mV resolution for a 1 V input signal range and 2 mW power consumption from a 3.3 V supply. The architecture can be scaled down to smaller feature sizes and lower supply voltages.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"4 1","pages":"6134-6137"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73160949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Efficient frame-level pipelined array architecture for full-search block-matching motion estimation 高效的帧级流水线阵列结构，用于全搜索块匹配运动估计
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2005-01-01 DOI: 10.1109/ISCAS.2005.1465230
Weifeng He, Yunlong Bi, Zhigang Mao
{"title":"Efficient frame-level pipelined array architecture for full-search block-matching motion estimation","authors":"Weifeng He, Yunlong Bi, Zhigang Mao","doi":"10.1109/ISCAS.2005.1465230","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465230","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"45 1","pages":"2887-2890"},"PeriodicalIF":0.0,"publicationDate":"2005-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83231783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A simplified algorithm of JPEG2000 rate control for VLSI implementation 一种用于VLSI实现的JPEG2000速率控制简化算法
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2005-01-01 DOI: 10.1109/ISCAS.2005.1466085
Xing Qin, Xiaolang Yan, Haitong Ge, Ye Yang
{"title":"A simplified algorithm of JPEG2000 rate control for VLSI implementation","authors":"Xing Qin, Xiaolang Yan, Haitong Ge, Ye Yang","doi":"10.1109/ISCAS.2005.1466085","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1466085","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"2 1","pages":"6316-6319"},"PeriodicalIF":0.0,"publicationDate":"2005-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78523540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An IF-sampling SC complex lowpass Sigma Delta modulator with high image rejection by capacitor sharing 一个中频采样SC复合低通σ δ调制器，具有高图像抑制电容共享
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1328401
W. Cheng, K. Pun, C. Chan, O. Choy
{"title":"An IF-sampling SC complex lowpass Sigma Delta modulator with high image rejection by capacitor sharing","authors":"W. Cheng, K. Pun, C. Chan, O. Choy","doi":"10.1109/ISCAS.2004.1328401","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328401","url":null,"abstract":"Lowpass complex sigma-delta (/spl Sigma//spl Delta/) modulators that have a built-in mixer can be used to digitize narrowband intermediate frequency (IF) signals in radios and cellular systems. A well-known problem of the complex modulators is the mismatches between the in-phase (I) and quadrature phase (Q) channels. In this paper, a technique of sharing the critical sampling and feedback capacitors between the I and Q channels of the modulator is proposed. As demonstrated by circuit simulations, the mismatch effect can be greatly suppressed and thus the image rejection performance can be improved. A 3/sup rd/ order complex modulator is designed with a 0.35/spl mu/m CMOS technology for a 10.7MHz IF input.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"6 1","pages":"1140-1143"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76829880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-power 10-bit continuous-time CMOS Sigma Delta A/D converter 低功耗10位连续时间CMOS Sigma Delta A/D转换器
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1328220
J. Nielsen, E. Bruun
{"title":"A low-power 10-bit continuous-time CMOS Sigma Delta A/D converter","authors":"J. Nielsen, E. Bruun","doi":"10.1109/ISCAS.2004.1328220","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328220","url":null,"abstract":"This paper presents the design of a third-order low-pass /spl Sigma//spl Delta/ analog-to-digital converter (ADC) employing a continuous-time (CT) loop filter. The loop filter is implemented using G/sub m/ - C integrators, where the transconductors are implemented using CMOS transistors only. System level as well as transistor level design issues for power efficiency is discussed. A prototype /spl Sigma//spl Delta/ ADC intended for weak biological signals restricted to bandwidths below 4 kHz has been manufactured in a standard 0.35 /spl mu/m CMOS technology. The ADC has a measured resolution of 10 bits and a dynamic range (DR) of 67 dB at a sampling rate of f/sub s/ = 1.4 MHz, while drawing a bias current of 60 /spl mu/A from a modest supply voltage of 1.8 V, thus consuming 108 /spl mu/W of power.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"7 1","pages":"417-420"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88789044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Direct RF sampling continuous-time bandpass Delta-Sigma A/D converter design for 3G wireless applications 直接射频采样连续时间带通Delta-Sigma A/D转换器设计的3G无线应用
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1328218
U. Koc, Jaesik Lee
{"title":"Direct RF sampling continuous-time bandpass Delta-Sigma A/D converter design for 3G wireless applications","authors":"U. Koc, Jaesik Lee","doi":"10.1109/ISCAS.2004.1328218","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328218","url":null,"abstract":"This paper presents the behavioral simulation of a fourth-order multi-bit continuous-time bandpass /spl Delta/-/spl Sigma/ analog-to-digital converter (ADC) for direct radio frequency (RF) conversion in multi-band 3G base stations. With a 2.1 GHz carrier frequency, the conventional method requires a sampling frequency greater than 8 GHz. To overcome the design complexity, jitter issue, and high power consumption anticipated for a design at such a high sampling-rate, we propose a new mirrored-image sampling technique to achieve targeted ADC performance at a much lower sampling rate. Detailed analysis of stability and signal-to-noise ratio (SNR) find the optimum DAC topology and design parameters. With an RZ33%-DAC, the ADC is capable of digitizing a 2.1 GHz RF signal with a 20 MHz band at 2.8 Gsamples/sec, and achieving a 87 dB SNR.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"2016 1","pages":"409-412"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87784691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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