IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems最新文献

Design of Compensator for Modified Multistage CIC-Based Decimation Filter with Improved Characteristics 改进特性的改进多级cic抽取滤波器补偿器设计

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2023-01-01 DOI: 10.1109/ISCAS46773.2023.10182010

G. Jovanovic-Dolecek

引用次数: 0

Using the Miller Theorem to Analyze Two-Stage Miller-Compensated Opamps 用米勒定理分析两阶段米勒补偿运算子

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2022-01-01 DOI: 10.1109/ISCAS48785.2022.9937345

R. S. A. Kumar

引用次数: 0

Analog processing by digital gates: fully synthesizable IC design for IoT interfaces 数字门模拟处理:物联网接口的完全可合成IC设计

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2020-01-01 DOI: 10.1109/ISCAS45731.2020.9180381

P. Crovetti, O. Aiello

引用次数: 0

A Parallel Radix-2 k FFT Processor using Single-Port Merged-Bank Memory 基于单端口合并存储的并行radix - 2k FFT处理器

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2019-05-26 DOI: 10.1109/ISCAS.2019.8702088

Wang Jian, Li Xianbin, Fan Guangteng, Tuo Zhouhui

引用次数: 1

Differential Fowler-Nordheim Tunneling Dynamical System for Attojoule Sensing and Recording. 用于焦耳传感和记录的差分Fowler-Nordheim隧道动力系统。

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2019-05-01 DOI: 10.1109/iscas.2019.8702685

Darshit Mehta, Barani Raman, Shantanu Chakrabartty

{"title":"Differential Fowler-Nordheim Tunneling Dynamical System for Attojoule Sensing and Recording.","authors":"Darshit Mehta, Barani Raman, Shantanu Chakrabartty","doi":"10.1109/iscas.2019.8702685","DOIUrl":"https://doi.org/10.1109/iscas.2019.8702685","url":null,"abstract":"Dynamical systems that evolve unidirectionally with respect to time provide a natural mechanism for implementing a time-domain, near-zero-threshold energy rectifier. In this paper we implement such a dynamical system using a pair of differential, leaky floating-gates and demonstrate that the circuit can sense and record signals of interest while compensating for environmental variations. A Fowler-Nordheim (FN) tunneling current has been used to implement the leakage process, which we experimentally show can be modulated by signals at energy levels below femtojoules. At this level of energy, the proposed FN-system could be self-powered using different types of biopotential energy sources like intra-cellular potentials, a feature that was not possible with previously reported recorders. Furthermore, the degree of modulation is shown to be a function of the input intensity as well as time-of-occurrence, which opens up the possibility of using reconstruction techniques to reconstruct the input signal from measurement of multiple sensing devices. Using devices fabricated in a 0.5 μm standard CMOS process, we demonstrate recording of 6 mV events with retention capability lasting over 30 minutes.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"2019 ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/iscas.2019.8702685","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"38325453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design Space Exploration for PCA Implementation of Embedded Learning in FPGAs fpga中嵌入式学习PCA实现的设计空间探索

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351540

Rodrigo Marino, J. M. Lanza-Gutiérrez, T. Riesgo, M. Holgado

引用次数: 1

A Reconfigurable 28/56 Gb/s PAM4/NRZ Dual-mode SerDes with Hardware-reuse 一种可重构的28/ 56gb /s PAM4/NRZ双模服务器

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351612

Heng Liu, Li Ding, J. Jin, Jianjun J. Zhou

{"title":"A Reconfigurable 28/56 Gb/s PAM4/NRZ Dual-mode SerDes with Hardware-reuse","authors":"Heng Liu, Li Ding, J. Jin, Jianjun J. Zhou","doi":"10.1109/ISCAS.2018.8351612","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351612","url":null,"abstract":"With the explosive growth of data rate demand, four-level pulse amplitude modulation (PAM4) SerDes standards are emerging, while binary non-return-to-zero (NRZ) standards still take the market. This paper proposes a novel dual-mode architecture designed for SerDes application data rate of up to 56 Gb/s with PAM4 modulation, and compatible to the legacy 28 Gb/s standards with NRZ modulation scheme. Attractively, with minor modification, the same hardware to send PAM4 signal can be used to implement a 28 Gb/s NRZ transmitter with 4-tap forward-feedback equalization (FFE), and meanwhile the PAM4 receiver can be easily reconfigured as a half-rate NRZ receiver with 1-tap loop-unrolled decision-feedback equalization (DFE). In addition, a digital duty-cycle correction (DCC) loop ensures the duty-cycle distortion (DCD) jitter introduced by half-rate transmitter architecture being less than 0.01UI in NRZ mode. The architecture is verified in 22nm CMOS FDSOI technology, and the simulation results across lossy channel show that the serial link transceiver can transmit 28/56 Gb/s with the eye opening of 400 mVpp in NRZ mode, and 150 mVpp in PAM4 mode in 1.2 V supply.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"33 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90172633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Effect of Switched-Capacitor CMFB on the Gain of Fully Differential Op-Amp for Design of Integrators 开关电容CMFB对积分器全差分运算放大器增益的影响

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351346

Joydeep Basu, P. Mandal

{"title":"Effect of Switched-Capacitor CMFB on the Gain of Fully Differential Op-Amp for Design of Integrators","authors":"Joydeep Basu, P. Mandal","doi":"10.1109/ISCAS.2018.8351346","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351346","url":null,"abstract":"Switched capacitor common-mode feedback (SC-CMFB) is a popular technique for stabilization of the output common-mode level of fully differential operational amplifiers. It provides advantages of excellent linearity across a wide amplifier output swing, lowest power consumption, and better feedback loop stability in contrast to continuous CMFB; and hence, are suitable for realization of high-gain wide-swing low-power opamps. But, its implementation demands careful consideration of some practical aspects, a number of which are well documented in literature. However, its detrimental effect on the amplifier's differential-mode gain is not quite explored. Equivalent resistive loading from the SC-CMFB is the reason for this effect, and is particularly important in op-amps meant to have large gain (like, the folded cascode). This SC-CMFB induced drop in amplifier dc-gain, and the consequent effect on the design of continuous and discrete-time integrators have been discussed together with pertinent analytical derivations and transistor level simulations. A few practical guidelines and circuit topologies for minimizing the gain reduction effect have also been provided.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"33 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87603900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

High Linearity SAR ADC for Smart Sensor Applications 用于智能传感器应用的高线性SAR ADC

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2018-05-04 DOI: 10.1109/ISCAS.2018.8350998

Hua Fan, Jingxuan Yang, F. Maloberti, Q. Feng, Dagang Li, Daqian Hu, Yuanjun Cen, H. Heidari

引用次数: 12

A Faster DiSH: Hardware Implementation of a Discrete Cell Signaling Network Simulator 一个更快的天线:一个离散小区信号网络模拟器的硬件实现

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2018-05-01 DOI: 10.1109/ISCAS.2018.8350960

Kevin Gilboy, Khaled Sayed, Niteesh Sundaram, Kara N. Bocan, Nataša Miškov-Živanov

引用次数: 2