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Direct RF sampling continuous-time bandpass Delta-Sigma A/D converter design for 3G wireless applications 直接射频采样连续时间带通Delta-Sigma A/D转换器设计的3G无线应用
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1328218
U. Koc, Jaesik Lee
{"title":"Direct RF sampling continuous-time bandpass Delta-Sigma A/D converter design for 3G wireless applications","authors":"U. Koc, Jaesik Lee","doi":"10.1109/ISCAS.2004.1328218","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328218","url":null,"abstract":"This paper presents the behavioral simulation of a fourth-order multi-bit continuous-time bandpass /spl Delta/-/spl Sigma/ analog-to-digital converter (ADC) for direct radio frequency (RF) conversion in multi-band 3G base stations. With a 2.1 GHz carrier frequency, the conventional method requires a sampling frequency greater than 8 GHz. To overcome the design complexity, jitter issue, and high power consumption anticipated for a design at such a high sampling-rate, we propose a new mirrored-image sampling technique to achieve targeted ADC performance at a much lower sampling rate. Detailed analysis of stability and signal-to-noise ratio (SNR) find the optimum DAC topology and design parameters. With an RZ33%-DAC, the ADC is capable of digitizing a 2.1 GHz RF signal with a 20 MHz band at 2.8 Gsamples/sec, and achieving a 87 dB SNR.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"2016 1","pages":"409-412"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87784691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A novel approach to the linearization of the differential transconductors 差分电感线性化的新方法
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1328371
M. Sadr
{"title":"A novel approach to the linearization of the differential transconductors","authors":"M. Sadr","doi":"10.1109/ISCAS.2004.1328371","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328371","url":null,"abstract":"In this paper, an economic approach to the linearization of the differential transconductors is proposed and compared with the source degeneration approach used to linearize the conventional differential pairs. The application of the resulted transconductor as a negative resistor is presented. The linearity, noise, and power performances are simulated, discussed, and compared with the conventional differential pair's.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"125 ","pages":"1020-1023"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/ISCAS.2004.1328371","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72419206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Dynamic nonlinear threshold decomposition algorithm for implementing stack filters 实现堆栈滤波器的动态非线性阈值分解算法
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2004-01-01 DOI: 10.1109/ISCAS.2004.1328828
Guangming Shi, Liya Sun, Honghua Liu, Daojun Huang
{"title":"Dynamic nonlinear threshold decomposition algorithm for implementing stack filters","authors":"Guangming Shi, Liya Sun, Honghua Liu, Daojun Huang","doi":"10.1109/ISCAS.2004.1328828","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328828","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"75 1","pages":"641-644"},"PeriodicalIF":0.0,"publicationDate":"2004-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74982185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new approach to generate hyperchaotic 3D-scroll attractors in a closed chain of Chua's circuits 蔡氏电路闭合链中产生超混沌三维涡旋吸引子的新方法
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2003-05-25 DOI: 10.1109/ISCAS.2003.1204955
D. Cafagna, G. Grassi
{"title":"A new approach to generate hyperchaotic 3D-scroll attractors in a closed chain of Chua's circuits","authors":"D. Cafagna, G. Grassi","doi":"10.1109/ISCAS.2003.1204955","DOIUrl":"https://doi.org/10.1109/ISCAS.2003.1204955","url":null,"abstract":"This paper presents an approach to generate new hyperchaotic attractors in a closed chain of Chua's circuits. By taking a ring of three circuits and by exploiting sine functions as non-linearities, the proposed technique enables 3D-scroll attractors to be generated. In particular, the paper shows that 3D-scroll dynamics can be easily designed by modifying six parameters related to the circuit nonlinearities.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"4 1","pages":"60-63"},"PeriodicalIF":0.0,"publicationDate":"2003-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76034441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Generation of multi-scroll chaos using second-order linear systems with hysteresis 带滞后的二阶线性系统产生多涡旋混沌
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2003-05-25 DOI: 10.1109/ISCAS.2003.1204961
F. Han, Xinghuo Yu, Guanrong Chen, Wenbo Liu, Yong Feng
{"title":"Generation of multi-scroll chaos using second-order linear systems with hysteresis","authors":"F. Han, Xinghuo Yu, Guanrong Chen, Wenbo Liu, Yong Feng","doi":"10.1109/ISCAS.2003.1204961","DOIUrl":"https://doi.org/10.1109/ISCAS.2003.1204961","url":null,"abstract":"This paper proposes a method of generating multi-scroll chaos using second-order linear systems with a hysteresis series. It shows that multi-scroll chaos can be produced in any direction in the phase plane. Furthermore, two-dimensional multi-scroll chaos can be generated as well. Both computer simulations and circuitry implementation have verified the multi-scroll chaos generation scheme.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"22 1","pages":"84-87"},"PeriodicalIF":0.0,"publicationDate":"2003-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77955607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient bit-serial systolic array for division over GF(2m) GF(2m)除法的高效位串行收缩阵列
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2003-01-01 DOI: 10.1109/ISCAS.2003.1205953
C. Kim, Soonhak Kwon, C. Hong, In-Gil Nam
{"title":"Efficient bit-serial systolic array for division over GF(2m)","authors":"C. Kim, Soonhak Kwon, C. Hong, In-Gil Nam","doi":"10.1109/ISCAS.2003.1205953","DOIUrl":"https://doi.org/10.1109/ISCAS.2003.1205953","url":null,"abstract":"In this paper, we propose a new bit-serial systolic array for computing division over GF(2\") using the standard basis representation. Based on a modified version of the binary extended GCD algorithm, we obtain a new data dependence graph (DG) and design an efficient bit-serial systolic array for division over GF(2\"). Analysis shows that the proposed array provides a significant reduction in both chip area and computational. delay time compared to previously proposed systolic arrays with the same U 0 format. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomials and has a unidirectional data flow and regularity, it is well suited for division circuit of elliptic curve cryptosystems (ECC).","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"520 1","pages":"252-255"},"PeriodicalIF":0.0,"publicationDate":"2003-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77055863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Complete practical synchronization of hyperchaotic circuits via a scalar signal 通过标量信号完成超混沌电路的实际同步
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2001-05-06 DOI: 10.1109/ISCAS.2001.921451
M. Brucoli, D. Cafagna, L. Carnimeo
{"title":"Complete practical synchronization of hyperchaotic circuits via a scalar signal","authors":"M. Brucoli, D. Cafagna, L. Carnimeo","doi":"10.1109/ISCAS.2001.921451","DOIUrl":"https://doi.org/10.1109/ISCAS.2001.921451","url":null,"abstract":"In this paper an approach to achieve a complete practical synchronization of hyperchaotic circuits with parameter mismatch via an impulsive scalar signal is presented. The chosen scalar signal is constituted by a sequence of samples of selected state variables alternatively transmitted for identical time frames. The approach is effectively applied to hyperchaotic circuits with parameter mismatch constituted by two bidirectionally coupled Chua's oscillators.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"29 1","pages":"791-794"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73216434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analytic limitations on sigma-delta modulator performance σ - δ调制器性能的解析限制
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2000-05-28 DOI: 10.1109/ISCAS.2000.856168
J. Harrison, N. Weste
{"title":"Analytic limitations on sigma-delta modulator performance","authors":"J. Harrison, N. Weste","doi":"10.1109/ISCAS.2000.856168","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856168","url":null,"abstract":"Analytic limitations on the noise transfer function of sigma-delta modulators are derived. The noise transfer function magnitude in decibels integrated against frequency sums to at least zero. An excess delay of one sample in the modulator feedback loop is found to be detrimental for lowpass modulators.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"70 1","pages":"746-749"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83795364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
SNDR sensitivity analysis for cascaded ΣΔ modulators 级联ΣΔ调制器的SNDR灵敏度分析
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2000-05-28 DOI: 10.1109/ISCAS.2000.856172
J. Morizio, M. Hoke, T. Koçak, C. Geddie, C. Hughes, J. Perry, S. Madhavapeddi, M. Hood, Ward Huffman, Takashi Okuda, H. Noda, Yasuo Morimoto, T. Kumamoto, M. Ishiwaki, H. Kondoh, Masao Nakaya, Takahiro Miki
{"title":"SNDR sensitivity analysis for cascaded ΣΔ modulators","authors":"J. Morizio, M. Hoke, T. Koçak, C. Geddie, C. Hughes, J. Perry, S. Madhavapeddi, M. Hood, Ward Huffman, Takashi Okuda, H. Noda, Yasuo Morimoto, T. Kumamoto, M. Ishiwaki, H. Kondoh, Masao Nakaya, Takahiro Miki","doi":"10.1109/ISCAS.2000.856172","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856172","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"25 1","pages":"765"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82776766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A receive path ΔΣ frequency to digital converter 一个接收路径ΔΣ频率到数字转换器
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2000-01-01 DOI: 10.1109/ISCAS.2000.856064
N. Filiol, T. Riley, M. Copeland, C. Plett
{"title":"A receive path ΔΣ frequency to digital converter","authors":"N. Filiol, T. Riley, M. Copeland, C. Plett","doi":"10.1109/ISCAS.2000.856064","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856064","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"41 1","pages":"331-334"},"PeriodicalIF":0.0,"publicationDate":"2000-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86407283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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