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Discrete cosine transform chip for real-time video applications 离散余弦变换芯片的实时视频应用
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 1990-05-01 DOI: 10.1109/ISCAS.1990.112447
U. Sjostrom, I. Defilippis, M. Ansorge, F. Pellandini
{"title":"Discrete cosine transform chip for real-time video applications","authors":"U. Sjostrom, I. Defilippis, M. Ansorge, F. Pellandini","doi":"10.1109/ISCAS.1990.112447","DOIUrl":"https://doi.org/10.1109/ISCAS.1990.112447","url":null,"abstract":"A new implementation of a flexible discrete cosine transform (DCT) chip is presented. The DCT chip is suitable for transforming real-time video images using 16-point*16-point subframes. Some special features of distributed arithmetic and an application-specific pipelined RAM memory are used to obtain a high-performance architecture. A full system for 2-D 16-point*16-point transforms is integrated on a single chip using a 2- mu m CMOS technology. The choice of a DCT algorithm, the architecture, and the implementation are examined.<<ETX>>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"89 1","pages":"1620-1623 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78386041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
High-frequency broadband amplifier ASIC design optimization using pole-zero compensation techniques 利用极零补偿技术优化高频宽带放大器专用集成电路设计
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 1990-05-01 DOI: 10.1109/ISCAS.1990.112698
M. Mercer, S. Burns
{"title":"High-frequency broadband amplifier ASIC design optimization using pole-zero compensation techniques","authors":"M. Mercer, S. Burns","doi":"10.1109/ISCAS.1990.112698","DOIUrl":"https://doi.org/10.1109/ISCAS.1990.112698","url":null,"abstract":"The relative performance of a hierarchy of broadband amplifier designs is examined. This design hierarchy consists of an emitter-coupled pair with resistive-shunt loading for baseline comparison, a compound-device amplifier, a compensated series-feedback amplifier, and an actively shunt-peaked amplifier. Both pole-zero compensated amplifiers incorporate compound devices. The circuits are fabricated on Tektronix Inc.'s analog array chip featuring the SH3 process with 6.5 f/sub T/ transistors.<<ETX>>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"43 1","pages":"3225-3229 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74994121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Maximum unconstrained loadability of power systems 电力系统的最大无约束负荷
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 1990-05-01 DOI: 10.1109/ISCAS.1990.112000
P. Sauer, Robin J. Evans, M. A. Pai
{"title":"Maximum unconstrained loadability of power systems","authors":"P. Sauer, Robin J. Evans, M. A. Pai","doi":"10.1109/ISCAS.1990.112000","DOIUrl":"https://doi.org/10.1109/ISCAS.1990.112000","url":null,"abstract":"It is shown that the maximum loadability of a power system depends on the allocation of load and generation. For a given load distribution by percentage and constant power factor, the maximum can be described by a scalar. The maximum value of this scalar depends on the generation scheduling. It is shown how the maximum loadability can be computed when there are no inequality constraints on the generation scheduling, line flows, or bus voltages. As in load flow, the set of nonlinear equations used does not have a unique solution. Further work is needed to see how the initial guess affects the solution.<<ETX>>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"126 1","pages":"1818-1821 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76577521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
High performance algorithms for digital signal processing AGC 数字信号处理的高性能算法
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 1990-05-01 DOI: 10.1109/ISCAS.1990.112424
G. Tavares, M. Piedade
{"title":"High performance algorithms for digital signal processing AGC","authors":"G. Tavares, M. Piedade","doi":"10.1109/ISCAS.1990.112424","DOIUrl":"https://doi.org/10.1109/ISCAS.1990.112424","url":null,"abstract":"New types of discrete-time automatic gain control (AGC) circuits are proposed. The AGCs are based on iterative processes, and both feedforward and feedback structures are considered for two different signal energy detectors: mean absolute deviation (MAD) and root mean square (RMS). The different algorithms were implemented on a digital signal processor, and experimental results are presented.<<ETX>>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"332 1","pages":"1529-1532 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76581481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Heterojunction bipolar transistors for high speed integrated circuits 高速集成电路用异质结双极晶体管
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 1990-05-01 DOI: 10.1109/ISCAS.1990.112530
C. Farley
{"title":"Heterojunction bipolar transistors for high speed integrated circuits","authors":"C. Farley","doi":"10.1109/ISCAS.1990.112530","DOIUrl":"https://doi.org/10.1109/ISCAS.1990.112530","url":null,"abstract":"The unique characteristics of heterojunction bipolar transistors (HBTs), their fabrication, state-of-the-art performance and applications are discussed. The future directions of HBT research and commercialization, including new material systems and advanced device structures, are addressed. HBTs are compared with other devices which operate in the GHz frequency range. These devices include bipolar junction transistors and field effect transistors. A discussion of HBT materials is presented.<<ETX>>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"101 1","pages":"2552-2556 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77372311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Finite series solution for loaded uniform RC lines 荷载均匀钢筋混凝土线的有限级数解
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 1990-05-01 DOI: 10.1109/ISCAS.1990.112489
G. P. Fiani
{"title":"Finite series solution for loaded uniform RC lines","authors":"G. P. Fiani","doi":"10.1109/ISCAS.1990.112489","DOIUrl":"https://doi.org/10.1109/ISCAS.1990.112489","url":null,"abstract":"The time-domain voltage step response of a loaded uniform RC line is derived in the form of a finite series. The locations of the poles are expressed as a function of the load parameters, yielding an approximate closed-form solution. Expressions for the delay time of RC lines are obtained. These apply to the cases of resistive, capacitive, and parallel R-C loads, the case of capacitive loading being in agreement with the published estimates for the delay time of capacitively loaded RC lines.<<ETX>>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"29 1","pages":"2381-2384 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77637083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Synchronous logic synthesis: circuit specifications and optimization algorithms 同步逻辑合成:电路规格和优化算法
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 1990-05-01 DOI: 10.1109/ISCAS.1990.112533
M. Damiani, G. De Micheli
{"title":"Synchronous logic synthesis: circuit specifications and optimization algorithms","authors":"M. Damiani, G. De Micheli","doi":"10.1109/ISCAS.1990.112533","DOIUrl":"https://doi.org/10.1109/ISCAS.1990.112533","url":null,"abstract":"Synchronous logic networks are characterized in terms of graphs, logic functions, and synchronous don't care conditions induced by the external and internal interconnection of the network. Algorithms to compute the don't care set for each local logic network. Algorithms to compute the don't care set for each logic function of the network from the synchronous don't care conditions that characterize the entire network are presented. Such local don't care conditions can be used to optimize locally each logic function to produce a smaller, faster, and better testable network.<<ETX>>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"59 1","pages":"2566-2570 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80475353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Dithering and its effects on sigma delta and multi-stage sigma delta modulation 抖动及其对σ δ和多级σ δ调制的影响
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 1990-05-01 DOI: 10.1109/ISCAS.1990.112043
W. Chou, R. Gray
{"title":"Dithering and its effects on sigma delta and multi-stage sigma delta modulation","authors":"W. Chou, R. Gray","doi":"10.1109/ISCAS.1990.112043","DOIUrl":"https://doi.org/10.1109/ISCAS.1990.112043","url":null,"abstract":"The spectrum of quantization noise in a dithered sigma-delta modulator and multistage sigma-delta modulator is derived under the constraint that the dithering signal does not cause overload. It is shown in the case of a simple sigma-delta modulation that no-overload dithering can smooth the noise spectrum and can make the binary quantization noise asymptotically uncorrelated with the input. It does not, however, make the noise white. In the case of multistage sigma-delta modulation with the appropriate dithering, the binary quantization noise becomes asymptotically white, even for a system with only two-stages. The signal-to-quantization-noise ratio is derived for sigma-delta and multistage sigma-delta oversampled analog-to-digital conversion with additive dithering. Simulation results are presented to support the theoretical analysis.<<ETX>>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"12 1","pages":"368-371 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81854704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Adaptive nonlinear state-space filters 自适应非线性状态空间滤波器
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 1990-05-01 DOI: 10.1109/ISCAS.1990.112673
X.Y. Gao, W. Snelgrove
{"title":"Adaptive nonlinear state-space filters","authors":"X.Y. Gao, W. Snelgrove","doi":"10.1109/ISCAS.1990.112673","DOIUrl":"https://doi.org/10.1109/ISCAS.1990.112673","url":null,"abstract":"An adaptive nonlinear state-space filter is introduced for nonlinear systems, especially those with long memories where adaptive nonlinear FIR filters are too expensive to use. Two methods for reduction in computation are developed to further facilitate its application in real-time signal processing. An adaptive linearization scheme for a class for nonlinear systems is presented. The ideas are applied to simulations of a loudspeaker with suspension nonlinearity, allowing both identification and linearization.<<ETX>>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"30 1","pages":"3122-3125 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84214857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An adaptive system identification method on bispectrum 一种基于双谱的自适应系统辨识方法
IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 1990-05-01 DOI: 10.1109/ISCAS.1990.112677
S. Alshebeili, A. Cetin, A. Venetsanopoulos
{"title":"An adaptive system identification method on bispectrum","authors":"S. Alshebeili, A. Cetin, A. Venetsanopoulos","doi":"10.1109/ISCAS.1990.112677","DOIUrl":"https://doi.org/10.1109/ISCAS.1990.112677","url":null,"abstract":"An adaptive technique for the identification of a linear system which is driven by white non-Gaussian noise is proposed. The system can be a nonminimum phase system. The adaptive identification technique is a least-mean-square type algorithm, and it is obtained by using the higher order cumulants of the system output. A simulation example is given.<<ETX>>","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"354 1","pages":"3138-3141 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84879308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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