一种高速、低功耗、低电压的全差分CMOS采样保持电路

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI:10.1109/ISCAS.2005.1465286

Tsung-Sum Lee, Chi-Chang Lu, S.H. Yu, J. Zhan

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引用次数: 5

摘要

提出了一种实现高速、低功耗、低电压全差分CMOS采样保持电路的新技术。全差分双采样设计减轻了采样速度和采样精度之间的权衡。仿真结果验证了该方法的潜在优势。

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A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully differential double-sampled design relaxes the trade-off between sampling speed and the sampling precision. Simulation results are given to demonstrate the potential advantage of the new technique.

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来源期刊

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

CiteScore

2.00

自引率

0.00%

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