Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits最新文献

A 66pW Discontinuous Switch-Capacitor Energy Harvester for Self-Sustaining Sensor Applications. 用于自维持传感器的66pW断续开关电容能量采集器。

Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits Pub Date : 2016-06-01 Epub Date: 2016-09-22 DOI: 10.1109/VLSIC.2016.7573490

Xiao Wu, Yao Shi, Supreet Jeloka, Kaiyuan Yang, Inhee Lee, Dennis Sylvester, David Blaauw

引用次数: 3

A 380pW Dual Mode Optical Wake-up Receiver with Ambient Noise Cancellation. 具有环境噪声消除功能的380pW双模光唤醒接收机。

Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits Pub Date : 2016-06-01 Epub Date: 2016-09-22 DOI: 10.1109/VLSIC.2016.7573481

Wootaek Lim, Taekwang Jang, Inhee Lee, Hun-Seok Kim, Dennis Sylvester, David Blaauw

引用次数: 14

IoT: The Impact of Things 物联网:事物的影响

Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits Pub Date : 2015-06-16 DOI: 10.1109/VLSIC.2015.7231361

Jolan De Boeck

引用次数: 14

A 120nW 8b Sub-ranging SAR ADC with Signal-Dependent Charge Recycling for Biomedical Applications. 120nw8b带信号依赖电荷回收的亚测距SAR ADC，用于生物医学应用。

Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits Pub Date : 2015-06-01 DOI: 10.1109/VLSIC.2015.7231327

Seokhyeon Jeong, Wanyeong Jung, Dongsuk Jeon, Omer Berenfeld, Hakan Oral, Grant Kruger, David Blaauw, Dennis Sylvester

引用次数: 14

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS 2.8mW/Gb/s 14Gb/s串行链路收发器，65nm CMOS

Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits Pub Date : 2015-01-01 DOI: 10.1109/VLSIC.2015.7231320

Saurabh Saxena, Guanghua Shu, R. Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, S. Kim, Woo-Seok Choi, P. Hanumolu

引用次数: 5

A 4.78mm2 fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation 一个4.78mm2的全集成神经调节SoC，结合64个采集通道，数字压缩和同步双重刺激

Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits Pub Date : 2014-06-10 DOI: 10.1109/VLSIC.2014.6858430

D. Yeager, W. Biederman, Nathan Narevsky, Jaclyn Leverett, R. Neely, J. Carmena, E. Alon, J. Rabaey

引用次数: 11

Stand by Leakage Power Reduction in Nanoscale Static CMOS VLSI Multiplier Circuits Using Self Adjustable Voltage Level Circuit 利用自调电压电平电路降低纳米级静态CMOS VLSI倍增电路的待机泄漏功率

Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits Pub Date : 2012-10-31 DOI: 10.5121/VLSIC.2012.3501

Deeprose Subedi

{"title":"Stand by Leakage Power Reduction in Nanoscale Static CMOS VLSI Multiplier Circuits Using Self Adjustable Voltage Level Circuit","authors":"Deeprose Subedi","doi":"10.5121/VLSIC.2012.3501","DOIUrl":"https://doi.org/10.5121/VLSIC.2012.3501","url":null,"abstract":"In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistorStatic Energy Recovery CMOS adder (SERF) circuits. The multiplier modules chosen were 4Bits Array, 4bits Carry Save and 4Bits Baugh Wooley multipliers. At first, the circuits were simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In all the multiplier architectures chosen, less standby leakage power was observed being consumed by the SERF adder based multipliers applied with SVL circuit. The stand-by leakage power dissipation is 1.16μwatts in Bits array multiplier with SERF Adder applied with SVL vs. 1.39μwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.16μwatts in Carry Save multiplier with SERF Adder applied with SVL vs. 1.4μwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.67μwatts in Baugh Wooley multiplier with SERF Adder applied with SVl circuit vs. 2.74μwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit.","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"48 1","pages":"1-12"},"PeriodicalIF":0.0,"publicationDate":"2012-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91396268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Leakage Power Reduction and Analysis of CMOS Sequential Circuits CMOS顺序电路的泄漏功率降低及分析

Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits Pub Date : 2012-02-29 DOI: 10.5121/VLSIC.2012.3102

M. Rani

引用次数: 37

Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology 面积高效的3.3GHZ锁相环，采用45NM VLSI技术

Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits Pub Date : 2011-03-24 DOI: 10.5121/VLSIC.2011.2110

U. Belorkar, S. Ladhake

引用次数: 3

A fully integrated 0.13 μm CMOS low-IF DBS satellite tuner using automatic signal-path gain and bandwidth calibration 一种完全集成的0.13 μm CMOS低中频DBS卫星调谐器，采用自动信号路径增益和带宽校准

Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits Pub Date : 2007-01-01 DOI: 10.1109/vlsic.2006.1705300

A. Maxim, R. Poorfard, Richard A. Johnson, P. Crawley, J. Kao, Z. Dong, M. Chennam, T. Nutt, D. Trager, M. Reid

{"title":"A fully integrated 0.13 μm CMOS low-IF DBS satellite tuner using automatic signal-path gain and bandwidth calibration","authors":"A. Maxim, R. Poorfard, Richard A. Johnson, P. Crawley, J. Kao, Z. Dong, M. Chennam, T. Nutt, D. Trager, M. Reid","doi":"10.1109/vlsic.2006.1705300","DOIUrl":"https://doi.org/10.1109/vlsic.2006.1705300","url":null,"abstract":"This paper presents the first low-IF fully integrated receiver for DBS satellite TV applications realized in 0.13 μm CMOS. A wideband ring oscillator based frequency synthesizer having a large frequency step was used to downconvert a cluster of channels to a coarsely defined low-IF frequency, while the second downconversion to baseband was performed in the digital domain. Eliminating the oscillator inductors reduced the parasitic magnetic coupling from the digital core, allowing a single-chip integration of the sensitive tuner and the noisy digital demodulator. A significant die area reduction was achieved by using a single oscillator to cover the entire satellite TV spectrum, while a noise attenuator was cascaded with the PLL loop filter to reduce the equivalent tuning gain. The low-IF architecture allowed a discrete-step AGC that improves both tuner noise and linearity performance. Tuner gain and IF corner frequency were calibrated using replica ring oscillators that are tuned up to the onset of oscillations. The tuner specifications include: 90 dB gain range, 9 dB noise figure at max gain, +25 dBm IIP3 at min gain, 1.3°rms integrated phase noise, <50 dBc spurs, 0.7 W power consumption from dual 1.8/3.3-V supplies, and 1.8 x 1.2 mm 2 die area.","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"85 1 1","pages":"897-921"},"PeriodicalIF":0.0,"publicationDate":"2007-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87668541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6