D. Yeager, W. Biederman, Nathan Narevsky, Jaclyn Leverett, R. Neely, J. Carmena, E. Alon, J. Rabaey
{"title":"一个4.78mm2的全集成神经调节SoC,结合64个采集通道,数字压缩和同步双重刺激","authors":"D. Yeager, W. Biederman, Nathan Narevsky, Jaclyn Leverett, R. Neely, J. Carmena, E. Alon, J. Rabaey","doi":"10.1109/VLSIC.2014.6858430","DOIUrl":null,"url":null,"abstract":"A 65nm CMOS 4.78mm\n 2 \nintegrated neuromodulation SoC consumes 417μW from a 1.2V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50Hz and engaging two stimulators with a pulse width of 250μs/phase, differential current of 150μA, and a pulse frequency of 100Hz. Compared to the state of the art, this represents the lowest area and power for the highest integration complexity achieved to date.","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"54 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A 4.78mm2 fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation\",\"authors\":\"D. Yeager, W. Biederman, Nathan Narevsky, Jaclyn Leverett, R. Neely, J. Carmena, E. Alon, J. Rabaey\",\"doi\":\"10.1109/VLSIC.2014.6858430\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 65nm CMOS 4.78mm\\n 2 \\nintegrated neuromodulation SoC consumes 417μW from a 1.2V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50Hz and engaging two stimulators with a pulse width of 250μs/phase, differential current of 150μA, and a pulse frequency of 100Hz. Compared to the state of the art, this represents the lowest area and power for the highest integration complexity achieved to date.\",\"PeriodicalId\":74899,\"journal\":{\"name\":\"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits\",\"volume\":\"54 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2014.6858430\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2014.6858430","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 4.78mm2 fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation
A 65nm CMOS 4.78mm
2
integrated neuromodulation SoC consumes 417μW from a 1.2V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50Hz and engaging two stimulators with a pulse width of 250μs/phase, differential current of 150μA, and a pulse frequency of 100Hz. Compared to the state of the art, this represents the lowest area and power for the highest integration complexity achieved to date.