Stand by Leakage Power Reduction in Nanoscale Static CMOS VLSI Multiplier Circuits Using Self Adjustable Voltage Level Circuit

In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistorStatic Energy Recovery CMOS adder (SERF) circuits. The multiplier modules chosen were 4Bits Array, 4bits Carry Save and 4Bits Baugh Wooley multipliers. At first, the circuits were simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In all the multiplier architectures chosen, less standby leakage power was observed being consumed by the SERF adder based multipliers applied with SVL circuit. The stand-by leakage power dissipation is 1.16μwatts in Bits array multiplier with SERF Adder applied with SVL vs. 1.39μwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.16μwatts in Carry Save multiplier with SERF Adder applied with SVL vs. 1.4μwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.67μwatts in Baugh Wooley multiplier with SERF Adder applied with SVl circuit vs. 2.74μwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit.