120nw8b带信号依赖电荷回收的亚测距SAR ADC，用于生物医学应用。

Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits Pub Date : 2015-06-01 DOI:10.1109/VLSIC.2015.7231327

Seokhyeon Jeong, Wanyeong Jung, Dongsuk Jeon, Omer Berenfeld, Hakan Oral, Grant Kruger, David Blaauw, Dennis Sylvester

{"title":"120nw8b带信号依赖电荷回收的亚测距SAR ADC，用于生物医学应用。","authors":"Seokhyeon Jeong, Wanyeong Jung, Dongsuk Jeon, Omer Berenfeld, Hakan Oral, Grant Kruger, David Blaauw, Dennis Sylvester","doi":"10.1109/VLSIC.2015.7231327","DOIUrl":null,"url":null,"abstract":"We present an 8-bit sub-ranging SAR ADC designed for bursty signals having long time periods with small code spread. A modified capacitive-DAC (CDAC) saves previous sample's MSB voltage and reuses it throughout subsequent conversions. This prevents unnecessary switching of large MSB capacitors as well as conversion cycles, reducing energy consumed in the comparator and digital logic and yielding total energy savings of 2.6×. In 0.18μm CMOS, the ADC consumes 120nW at 0.6V and 100kS/s with 46.9dB SNDR.","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"2015 ","pages":"C60-C61"},"PeriodicalIF":0.0000,"publicationDate":"2015-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/VLSIC.2015.7231327","citationCount":"14","resultStr":"{\"title\":\"A 120nW 8b Sub-ranging SAR ADC with Signal-Dependent Charge Recycling for Biomedical Applications.\",\"authors\":\"Seokhyeon Jeong, Wanyeong Jung, Dongsuk Jeon, Omer Berenfeld, Hakan Oral, Grant Kruger, David Blaauw, Dennis Sylvester\",\"doi\":\"10.1109/VLSIC.2015.7231327\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present an 8-bit sub-ranging SAR ADC designed for bursty signals having long time periods with small code spread. A modified capacitive-DAC (CDAC) saves previous sample's MSB voltage and reuses it throughout subsequent conversions. This prevents unnecessary switching of large MSB capacitors as well as conversion cycles, reducing energy consumed in the comparator and digital logic and yielding total energy savings of 2.6×. In 0.18μm CMOS, the ADC consumes 120nW at 0.6V and 100kS/s with 46.9dB SNDR.\",\"PeriodicalId\":74899,\"journal\":{\"name\":\"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits\",\"volume\":\"2015 \",\"pages\":\"C60-C61\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1109/VLSIC.2015.7231327\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2015.7231327\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2015.7231327","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 14

摘要

我们提出了一个8位亚测距SAR ADC，设计用于具有长时间周期和小码宽的突发信号。改进的电容式dac (CDAC)保存了之前样本的MSB电压，并在随后的转换中重用它。这可以防止不必要的大型MSB电容器切换以及转换周期，减少比较器和数字逻辑中的能量消耗，并产生2.6倍的总节能。在0.18μm CMOS中，ADC在0.6V和100kS/s下功耗为120nW, SNDR为46.9dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

A 120nW 8b Sub-ranging SAR ADC with Signal-Dependent Charge Recycling for Biomedical Applications.

查看原文本刊更多论文

A 120nW 8b Sub-ranging SAR ADC with Signal-Dependent Charge Recycling for Biomedical Applications.

We present an 8-bit sub-ranging SAR ADC designed for bursty signals having long time periods with small code spread. A modified capacitive-DAC (CDAC) saves previous sample's MSB voltage and reuses it throughout subsequent conversions. This prevents unnecessary switching of large MSB capacitors as well as conversion cycles, reducing energy consumed in the comparator and digital logic and yielding total energy savings of 2.6×. In 0.18μm CMOS, the ADC consumes 120nW at 0.6V and 100kS/s with 46.9dB SNDR.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits

自引率

0.00%

发文量