2021 IEEE Applied Power Electronics Conference and Exposition (APEC)最新文献_第7页

Online Monitoring of Degradation Sensitive Electrical Parameters in Inverter Operation for SiC-MOSFETs sic - mosfet逆变器运行中退化敏感电参数的在线监测

2021 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2021-06-14 DOI: 10.1109/APEC42165.2021.9487142

Kevin Muñoz Barcón, K. Sharma, M. Nitzsche, I. Kallfass

引用次数: 5

A New Cascaded SuperCascode High Voltage Power Switch 一种新型级联式supercascade高压电源开关

2021 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2021-06-14 DOI: 10.1109/APEC42165.2021.9487049

U. Mehrotra, D. Hopkins

{"title":"A New Cascaded SuperCascode High Voltage Power Switch","authors":"U. Mehrotra, D. Hopkins","doi":"10.1109/APEC42165.2021.9487049","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487049","url":null,"abstract":"Medium Voltage (MV), High Current (HC) switches are growing in demand for MV applications in land, sea and air transport, fast charging, renewable energy, and a host of applications in pulsed power, e.g. solid-state protection. However, widespread adoption of commercially available MV-HC modules is limited due to retracted dynamic performance from paralleling many high voltage, low current semiconductors. The associated cost is relatively high because of low yield, and expensive material and fabrication. An alternative is series connection of Low Voltage (LV)-HC semiconductors to form a SuperCascode (SC) power switch. This paper introduces a Cascaded SuperCascode (CSC) power switch topology that scales to very high voltages (>100 kV) or applied to optimize previously reported MV SCs to achieve higher switching speed, reduced balancing network size and lower switching losses. This paper describes the design of the balancing network for optimized CSC switch switching speed, and provides simulation and test results of a 6.5 kV power switch. The switch simulated to show a 4.5x improvement in switching speed (avg of Ton and Toff), 40% reduction in switching losses, 60% net charge reduction in network capacitors (i.e. size reduction) and superior avalanche energy management for greater short circuit performance compared to other SCs. The switch was fabricated and tested showing 408 mΩ, 0.7 mA @ 4.8 kV and 23ns rise and 50ns fall in current at 4kV for 50A switching from double-pulse testing (DPT).","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80828769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

High Gain Interleaved Stacked Boost Converter 高增益交错堆叠升压转换器

2021 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2021-06-14 DOI: 10.1109/APEC42165.2021.9487075

S. S. Ghumman, P. Lehn, M. Pathmanathan

引用次数: 0

Two-Switch Zeta-Based Single-Phase Rectifier With Inherent Power Decoupling And No Extra Buffer Circuit 基于zeta的双开关单相整流器，具有固有的功率去耦和无额外缓冲电路

2021 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2021-06-14 DOI: 10.1109/APEC42165.2021.9487472

Robson de Souza Donato, Marlius Hudson de Aguiar, Roniel Ferreira Cruz, M. Vitorino, M. B. de Rossiter Corrêa

引用次数: 1

A Novel Decentralized PWM Interleaving Technique for Ripple Minimization in Series-stacked DC-DC Converters 串联堆叠DC-DC变换器纹波最小化的分散PWM交织技术

2021 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2021-06-14 DOI: 10.1109/APEC42165.2021.9487386

S. Dutta, B. Majmunović, S. Mukherjee, R. Mallik, Gab-Su Seo, D. Maksimović, Brian B. Johnson

{"title":"A Novel Decentralized PWM Interleaving Technique for Ripple Minimization in Series-stacked DC-DC Converters","authors":"S. Dutta, B. Majmunović, S. Mukherjee, R. Mallik, Gab-Su Seo, D. Maksimović, Brian B. Johnson","doi":"10.1109/APEC42165.2021.9487386","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487386","url":null,"abstract":"Cascaded dc-dc converters are commonly used in applications where distributed energy sources or loads are connected to elevated voltage levels for power transfer. In such systems, it is advantageous to minimize the ripple on the bus current and voltage by proper phase shifting of the pulse-width modulation (PWM) pulses among the converters via a method known as interleaving. Existing approaches use either a centralized controller or separate communication lines among the stacked converters to control their relative PWM switch transitions. The key drawbacks are that these methods entail significant wiring, the central controller acts as a single point of failure, and implementation on very large numbers of units is impractical. In this paper, we introduce a decentralized interleaving control (DIC) strategy that acts on local current measurements at every converter and achieves communication-free PWM interleaving among the series-stacked converters. The proposed controller is simple in structure and is shown to converge asymptotically to the interleaved state irrespective of clock drifts among the digital signal processors. Experimental results are provided for a system of five series-connected converters showing a 10× reduction in the current ripple compared to normal operation.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82399287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Common-Mode-Free Bidirectional Three-Phase PFC-Rectifier for Non-Isolated EV Charger 用于非隔离式EV充电器的无共模双向三相pfc整流器

2021 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2021-06-14 DOI: 10.1109/APEC42165.2021.9487462

B. Strothmann, F. Schafmeister, J. Böcker

{"title":"Common-Mode-Free Bidirectional Three-Phase PFC-Rectifier for Non-Isolated EV Charger","authors":"B. Strothmann, F. Schafmeister, J. Böcker","doi":"10.1109/APEC42165.2021.9487462","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487462","url":null,"abstract":"DC-DC converters for on-board chargers (OBC) of electrical vehicles are usually galvanically isolated allowing modular single-phase PFC front-end solutions, but require transformers which are more bulky, costly and lossy than inductors of non-isolated DC-DCs. Furthermore, for vehicle-to-grid applications, bidirectional converters with transformers are generally more complex and have a higher count on semiconductor switches than transformerless solutions. However, when using non-isolated DC-DC converters within an OBC, the large common-mode (CM) capacitance comprising capacitive parasitics of the traction battery as well as explicit Y-capacitors connecting the high-voltage DC-system (HV-system) within specific HV-loads to ground has to be considered. For the PFC front-end stage, when supplied from the three-phase mains this means that generation of high-frequency and high-amplitude CM voltages, as it is common e.g. with the conventional six-switch full-bridge converter, has to be strictly avoided. For this reason, a modified topology is suggested leading to a different mode of operation and to a very low common-mode noise behaviour: The three-phase four-wire full-bridge PFC with split DC-link, whose midpoint is connected to the mains neutral provides very stable potentials at the DC-link rails and therefore it can be classified as Zero-CM-topology.For dedicated single-phase operation, as required for most OBC, an additional balancing leg may be added to the topology to reduce the required DC-link capacitance and allow non-electrolytic capacitors.The function of the bidirectional Zero-CM three-phase four-wire full-bridge PFC was verified by simulation and on an 11 kW-laboratory sample. The power factor is above 0.999 and an efficiency of 98 % is measured.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81027037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Dynamic Performance Improvement of Model-Based Capacitor Voltage Control for Single-Phase STATCOM with Reduced Capacitance 基于模型的减容单相STATCOM电容电压控制动态性能改进

2021 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2021-06-14 DOI: 10.1109/APEC42165.2021.9487055

Motoki Akihiro, Tomoyuki Mannen, T. Isobe

引用次数: 0

A Control Method for THD Minimization in High Power Density Vienna-type Rectifier 高功率密度维也纳整流器中THD最小化的控制方法

2021 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2021-06-14 DOI: 10.1109/APEC42165.2021.9487383

M. Mobarrez, A. Kadavelugu, Utkarsh Raheja, H. Suryanarayana

{"title":"A Control Method for THD Minimization in High Power Density Vienna-type Rectifier","authors":"M. Mobarrez, A. Kadavelugu, Utkarsh Raheja, H. Suryanarayana","doi":"10.1109/APEC42165.2021.9487383","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487383","url":null,"abstract":"Among many existing converter topologies for active power factor correction, Vienna-type rectifiers are widely used in high-power three-phase applications such as electric vehicle chargers, uninterruptible power supplies and telecommunication power supplies. The Vienna rectifier offers many advantages compared to the traditional two-level rectifier, which include: three-level switching, reduced switching losses, shoot-through immunity and lower conducted common-mode EMI. However, distortion of input currents is an inherent drawback of this topology due to the discontinuity of the switching current around zero-crossing. This issue can be resolved by oversizing the filter inductors or increasing the switching frequency. However, these approaches reduce power density, increase cost and switching losses of the converter. In this paper, we propose a control method that can reduce the total harmonic distortion (THD) of the input currents without adding to the costs or losses of the converter. The proposed control architecture is verified on a three-phase 12 kW SiC-based Vienna rectifier.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83166124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Optimization of Electric-Field Grading Plates in a PCB-Integrated Bus Bar for a High-Density 10 kV SiC MOSFET Power Module 高密度10kv SiC MOSFET功率模块pcb集成母线中电场分级板的优化

2021 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2021-06-14 DOI: 10.1109/APEC42165.2021.9487102

M. Cairnie, C. Dimarino

引用次数: 1

Multiphysics-based Design Optimization of Medium Frequency Transformer with Experimental Validation 基于多物理场的中频变压器设计优化及实验验证

2021 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2021-06-14 DOI: 10.1109/APEC42165.2021.9487267

T. Olowu, H. Jafari, A. Sarwat

{"title":"Multiphysics-based Design Optimization of Medium Frequency Transformer with Experimental Validation","authors":"T. Olowu, H. Jafari, A. Sarwat","doi":"10.1109/APEC42165.2021.9487267","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487267","url":null,"abstract":"In resonant converters, medium frequency transformers (MFTs) are used to provide galvanic isolation between the primary and secondary converters. The overall power transfer efficiency of the converter topology largely depends on the efficiency of the MFTs. Existing methods in literature often estimated the MFT’s parameters analytically and also do not optimize the MFTs using all the physics models that describe the practical behaviour of the MFT during operation. These approaches introduces some errors consequently increasing the discrepancies between the simulation and experimental results. Also many optimization algorithms often neglect the material cost of the MFT during optimization. This paper proposes a FEA-based multi-physics (time-harmonic electromagnetic, thermal and fluid models) coupled design optimization for MFT. The proposed optimization minimizes the total transformer power loss, and cost while maximizing its power density. The core dimensions, number of turns and the switching frequency are obtained from the Pareto optimal solutions. A case study of a 5kW, 110/110V transformer is investigated. The optimization results is compared with experimental measurements. The experimental results are in very good agreement with the optimization results which shows that a higher level of accuracy can be achieved using this approach.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86702459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0