{"title":"高密度10kv SiC MOSFET功率模块pcb集成母线中电场分级板的优化","authors":"M. Cairnie, C. Dimarino","doi":"10.1109/APEC42165.2021.9487102","DOIUrl":null,"url":null,"abstract":"A finite element method (FEM) driven, automated numerical optimization technique is used to design field grading structures in a PCB-integrated bus bar for a 10 kV wirebondless silicon-carbide (SiC) MOSFET power module. Due to the ultra-high-density of the power module, and close proximity of the high-voltage power terminals, PCB embedded field grading structures are used to manipulate the high intensity electric field and reduce field crowding. Two PCBs are designed and built, one using a conventional, manual design approach, where design parameters are swept individually and the impact is assessed graphically, and one with the proposed optimization technique. The PCB developed with the proposed technique achieved a 30% higher partial discharge inception voltage (PDIV) and reduced the design cycle time from a few weeks to a few days. The problem formulation and cost function are scalable to allow for wide applicability in the design of other high-voltage, high-density systems.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Optimization of Electric-Field Grading Plates in a PCB-Integrated Bus Bar for a High-Density 10 kV SiC MOSFET Power Module\",\"authors\":\"M. Cairnie, C. Dimarino\",\"doi\":\"10.1109/APEC42165.2021.9487102\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A finite element method (FEM) driven, automated numerical optimization technique is used to design field grading structures in a PCB-integrated bus bar for a 10 kV wirebondless silicon-carbide (SiC) MOSFET power module. Due to the ultra-high-density of the power module, and close proximity of the high-voltage power terminals, PCB embedded field grading structures are used to manipulate the high intensity electric field and reduce field crowding. Two PCBs are designed and built, one using a conventional, manual design approach, where design parameters are swept individually and the impact is assessed graphically, and one with the proposed optimization technique. The PCB developed with the proposed technique achieved a 30% higher partial discharge inception voltage (PDIV) and reduced the design cycle time from a few weeks to a few days. The problem formulation and cost function are scalable to allow for wide applicability in the design of other high-voltage, high-density systems.\",\"PeriodicalId\":7050,\"journal\":{\"name\":\"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APEC42165.2021.9487102\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APEC42165.2021.9487102","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimization of Electric-Field Grading Plates in a PCB-Integrated Bus Bar for a High-Density 10 kV SiC MOSFET Power Module
A finite element method (FEM) driven, automated numerical optimization technique is used to design field grading structures in a PCB-integrated bus bar for a 10 kV wirebondless silicon-carbide (SiC) MOSFET power module. Due to the ultra-high-density of the power module, and close proximity of the high-voltage power terminals, PCB embedded field grading structures are used to manipulate the high intensity electric field and reduce field crowding. Two PCBs are designed and built, one using a conventional, manual design approach, where design parameters are swept individually and the impact is assessed graphically, and one with the proposed optimization technique. The PCB developed with the proposed technique achieved a 30% higher partial discharge inception voltage (PDIV) and reduced the design cycle time from a few weeks to a few days. The problem formulation and cost function are scalable to allow for wide applicability in the design of other high-voltage, high-density systems.