高密度10kv SiC MOSFET功率模块pcb集成母线中电场分级板的优化

M. Cairnie, C. Dimarino
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引用次数: 1

摘要

采用有限元法(FEM)驱动的自动化数值优化技术,设计了用于10kv无线碳化硅(SiC) MOSFET功率模块的pcb集成母线的现场分级结构。由于功率模块的超高密度,以及高压电源端子的靠近,采用PCB嵌入式场级结构来控制强电场,减少场拥挤。设计和制造了两个pcb,一个使用传统的手动设计方法,其中设计参数单独扫描并以图形方式评估影响,另一个使用所提出的优化技术。采用该技术开发的PCB实现了30%高的局部放电起始电压(PDIV),并将设计周期从几周缩短到几天。问题公式和成本函数是可扩展的,可以广泛适用于其他高压,高密度系统的设计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimization of Electric-Field Grading Plates in a PCB-Integrated Bus Bar for a High-Density 10 kV SiC MOSFET Power Module
A finite element method (FEM) driven, automated numerical optimization technique is used to design field grading structures in a PCB-integrated bus bar for a 10 kV wirebondless silicon-carbide (SiC) MOSFET power module. Due to the ultra-high-density of the power module, and close proximity of the high-voltage power terminals, PCB embedded field grading structures are used to manipulate the high intensity electric field and reduce field crowding. Two PCBs are designed and built, one using a conventional, manual design approach, where design parameters are swept individually and the impact is assessed graphically, and one with the proposed optimization technique. The PCB developed with the proposed technique achieved a 30% higher partial discharge inception voltage (PDIV) and reduced the design cycle time from a few weeks to a few days. The problem formulation and cost function are scalable to allow for wide applicability in the design of other high-voltage, high-density systems.
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