2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)最新文献

{"title":"Comparing and Benchmarking Fatigue Behaviours of Various SAC Solders under Thermo-Mechanical Loading","authors":"Joshua Adeniyi Depiver, S. Mallik, E. Amalu","doi":"10.1109/ESTC48849.2020.9229699","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229699","url":null,"abstract":"While the fatigue behaviours (including fatigue life predictions) of lead-free solder joints have been extensively researched in the last 15 years, these are not adequately compared and benchmarked for different lead-free solders that are being used. As more and more fatigue properties of lead-free solders are becoming available, it is also critical to know how fatigue behaviours differ under different mathematical models. This paper addresses the challenges and presents a comparative study of fatigue behaviours of various mainstream lead-free Sn-Ag-Cu (SAC) solders and benchmarked those with lead-based eutectic solder. Creep-induced fatigue and fatigue life of lead-based eutectic Sn63Pb37 and four lead-free SAC solder alloys: SAC305, SAC387, SAC396 and SAC405 are analysed through simulation studies. The Anand model is used to simulate the inelastic deformation behaviour of the solder joints under accelerated thermal cycling (ATC). It unifies the creep and rate-independent plastic behaviour and it is used to predict the complex stress-strain relationship of solders under different temperatures and strain rates, which are required in the prediction of fatigue life using the fatigue life models such as Engelmaier, Coffin-Mason and Solomon as the basis of our comparison. The ATC was carried out using temperature range from −40°C to 150°C. The fatigue damage propagation is determined with finite element (FE) simulation, which allows virtual prototyping in the design process of electronics devices. The simulation was carried out on a BGA (36 balls, 6 × 6 matrix) mounted onto Cu padded substrate. Results are analysed for plastic strain, Von mises stress, strain energy density, and stress-strain hysteresis loop. The simulation results show that the fatigue behaviours of lead-based eutectic Sn63Pb37 solder is comparable to those of lead-free SAC solders. Among the four SAC solders, SAC387 consistently produced higher plastic strain, strain energy and stress than the other solders. The fatigue life’s estimation of the solder joint was investigated using Engelmaier, Coffin-Manson, and Solomon models. Results obtained show that SAC405 has the highest fatigue life (25.7, 21.1 and 19.2 years) followed by SAC396 (18.7, 20.3 and 17.9 years) and SAC305 (15.2, 13.6 and 16.2 years) solder alloys respectively. Predicting the fatigue life of these solder joints averts problems in electronics design for reliability and quality, which if not taken care of, may result in lost revenue. Predictive fatigue analysis can also considerably reduce premature failure, and modern analysis technique such as one used in this research is progressively helping to provide comprehensive product life expectancy data.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"5 1","pages":"1-11"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88952216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Carbon nanotubes based on-chip supercapacitors with improved areal energy density","authors":"Chengjun Yu, Xuyuan Chen","doi":"10.1109/ESTC48849.2020.9229835","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229835","url":null,"abstract":"Supercapacitors or electrochemical capacitors, as a kind of energy storage devices, have been intensively studied for decades as its combination of high energy density and high power density with long cycle life. The integration of on-chip supercapacitors with Si-compatible processes will further expand their application in electronic systems. Among them, porous carbon materials are quite promising, because the porous carbon owns high surface area with optimised porosity, high electrical conductivity and good electrochemical stability. It was previously reported by our group that high surface area Si-grass withcarbon nanotubes (CNTs) deposition via atmospheric pressure chemical vapor deposition (APCVD) could exhibit high areal energy density for supercapacitor application. In this paper, further improvement in areal energy density is achieved by solution-based catalyst loading into the CNTs network and subsequent CNTs growth via APCVD method in the tube furnace. The mass loading of carbon active materials are enhanced as compact integration of two dense CNT layers to achieve the high areal capacitance 159 mF/cm2 at 5 mV/s with 62 mF/cm2 increasing from one CNT layer, and the main electricity storage mechanism is still electrochemical double layer (ECDL) with the rectangle structure showed in the cyclic voltammetry (CV) curves, which shows these supercapacitors remain the high power properties. These findings demonstrated that CNT based supercapacitors are still competitive in areal energy density with improved mass loading.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"51 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90847021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Imprint-Through Mold Via (i-TMV) with Highly-Effective Electromagnetic Interference Shielding for RF devices","authors":"T. Shibata, S. Yoneda, Xinrong Li, N. Suzuki, T. Nonaka","doi":"10.1109/ESTC48849.2020.9229755","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229755","url":null,"abstract":"This work presents the imprint-thorough mold via (i-TMV) concept applicable for compartmental level electromagnetic interference (EMI) shielding. The i-TMV structure could be successfully fabricated by imprinting with the silicon master and filling with the conductive paste. We have fabricated a daisy-chained i-TMV test vehicle and it showed good connectivity. In order to study the EMI shielding properties, the electric field simulation was performed. Single and triple-array structures were modeled based on the fabricated test vehicle, and compared with the structure without via array. The result showed that the i-TMV could provide excellent EMI shielding.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"134 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87596719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thinning and readout during bending of a custom silicon IC","authors":"R. Langoy, M. Mager, A. T. Nguyen, J. Lien","doi":"10.1109/ESTC48849.2020.9229845","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229845","url":null,"abstract":"This contribution presents a solution on how to interconnect, thin and bend a monolithic integrated circuit (IC) for use in the Inner Tracker System v3 (ITS3) of the ALICE experiment at the European Organization for Nuclear Research (CERN). Verification of the system operations was done by building a dedicated readout system. The technology is demonstrated by thinning a 30 mm x 15 mm x 130 µm monolithic active pixel sensor to 45 µm and curving the chip to a radius of 20 mm while monitoring the internal registers and current consumption.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"1 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85438402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability Testing of FCCSP Packages for Automotive Applications","authors":"K. Meier, L. Wambera, B. Boehme, Christian Goetze, S. Capecchi, J. Paul, M. Wieland, K. Bock","doi":"10.1109/ESTC48849.2020.9229734","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229734","url":null,"abstract":"Autonomous driving and car to car or car to infrastructure communication applications are pursuing and demand for a detailed understanding of the reliability of electronics. This work focuses on reliability analysis of flip-chip chip scale packages (FCCSP) for such as automotive electronics applications. Reliability investigation is accomplished by means of temperature cycling on board level (TCoB) since it is strongly recommended to apply such tests during the package development phase. Tests have been done on FCCSP components. The board level interconnects are solder joints with a BGA pitch of 0.4 mm. The packages have been assembled to custom test boards using SnAgCu solder alloy. Temperature cycling was done at -40/125 °C according to the AEC-Q100 standard. Test board development was done to enable harsh test conditions and to cover advanced use requirements, e.g. by selecting a high-Tg material. The entire test setup enables in-situ monitoring of resistance and leakage currents. The tested packages have been manufactured using a flip-chip CSP assembly technology and Cu-pillar first level interconnects. As electronics qualification procedures require passing at least 500 TC cycles but the AEC even ask to pass 1,000 cycles, the aim of this study was to investigate the health of the first and second level interconnects of the FCCSP package after an intermediate cycle count of 750. The stress which the second level interconnects are exposed to was accelerated. Therefore, the board design considered SMD defined pads with a rather small pad diameter. In addition, consecutive electrical read-outs were used to prove if an offline monitoring of selected I/Os can be used to track the overall specimen health throughout the experiment. Analyses of the samples are in progress including extensive cross sectioning. Though no damages were seen at the BEoL structures nor first level interconnects, severe damage of the second level interconnects is proven and certainly caused by the specific board pad design. In addition, board design features such as trace routing seem to have an influence on the second level solder joint reliability as well. However, based on the accomplished number of TCoB cycles and analysis results a high package level robustness of the FCCSP can be concluded and proposals for the board design can be derived.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"24 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76687681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electroplating of Pd/Sn Multilayers for Reactive Bonding in Packaging and Assembly Applications","authors":"S. Hertel, K. Vogel, M. Wiemer, T. Otto","doi":"10.1109/ESTC48849.2020.9229651","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229651","url":null,"abstract":"The reactive bonding is a joining technology carried out at room temperature. With further diversity of electronic modules, the joining temperature becomes more important for heat sensitive componentsIn this paper, the electroplating of palladium (Pd) and tin (Sn) reactive multilayer systems for the use in electronic assembly is described. The Pd/Sn multilayers can be deposited reproducible on silicon chips using two separate metal electrolytes. It is shown that 425 nm and 510 nm bilayer periods produces ignitable reactive systems. The bonding can be achieved with 60 bilayers of 425 nm bilayer period at a reaction velocity of 5.7 m/s.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"25 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83420201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bi Behaviour in Au–(In–Bi) SLID Bonding","authors":"S. L. Kuziora, Hoang-Vu Nguyen, Per Kristian Bolstad, K. Aasmundtveit","doi":"10.1109/ESTC48849.2020.9229784","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229784","url":null,"abstract":"Au–(In–Bi) solid-liquid interdiffusion bonding (SLID) has shown potential for assembly of temperature-sensitive materials, such as poled piezoelectric and composite materials. Successful bonds can be made using Au–(In–Bi) SLID bonding at a low temperature of 120 °C. This work focuses on studying the behaviour of Bi in the Au–(In–Bi) SLID system. Thin-film (1 μm) eutectic In–Bi (78.5 at% In) is deposited as the intermediate layer for bonding by electron-beam evaporation. Bonding at 120 °C in atmosphere produced bonds with Bi inclusions. The Bi inclusions were characterized at various bonding times using cross-sectional measurements. The inclusions indicated poor bonding to Au, meaning asymmetric bonds where Bi inclusions are in direct contact with Au are mechanically weaker compared to a symmetric bond where there is no contact between the Au and Bi inclusions. The average size of the Bi inclusions in the bondline increased with bonding time. However, the large variance between the observed number of inclusions means more analysis is needed to confirm that this is mainly a result of coalescence as opposed to further segregation of the Bi from the liquid In–Bi phase as bonding time is increased.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"14 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85084079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A System Level SI-PI co-simulation of LPDDR4x at 4267Mbps Speed","authors":"Ashish Gupta, Rajiv Panigrahi, Afsar Y. Sayed, Vinay K. Naik, Sheetal Jain, Sanjeev K. Gupta","doi":"10.1109/ESTC48849.2020.9229705","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229705","url":null,"abstract":"A system level SI-PI co-simulation of LPDDR4x 4267 Mbps is presented. Power Supply Induced Jitter (PSIJ) is estimated based on noise numbers of IO and core supplies. This PSIJ is fed into signal integrity simulation with ideal power to evaluate write and read margins. Layout and stackup optimization of both package and PCB is discussed in detail. Eye height and Eye width are measured and compared with Tx and Rx specification to conclude good margins.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"55 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77675186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bipolar photodiode module operated at 4 K","authors":"E. Bardalen, J. Nissilä, T. Fordell, B. Karlsen, O. Kieler, P. Ohlckers","doi":"10.1109/ESTC48849.2020.9229695","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229695","url":null,"abstract":"An optoelectronic module for generating high frequency bipolar current pulses at 4 K was developed. Bipolar signals are generated by connecting a pair of photodiodes in series to coplanar waveguides on silicon. The transmission line pulse propagation was simulated in COMSOL. A planar optical fiber connector was fabricated, where the end fiber faces where angle polished to reflect the beam perpendicular to the fiber. An assembled prototype was fabricated by flip-chip bonding photodiodes to the silicon photodiode carrier. The optical connector was aligned and bonded using epoxy. The prototype was tested using a mode-locked laser producing pulses with sub-20 ps pulses. Bipolar output pulses were generated at 4 K and measured using an oscilloscope. The measured output pulses were affected by ringing and were broader than the reference signal. Comparison with simulations indicate that the ringing was caused by reflections at wirebonds.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"178 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73257677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Graphene based thermal management system for battery cooling in electric vehicles","authors":"Ya Liu, T. Thiringer, Nan Wang, Yifeng Fu, Hongbing Lu, Johan Liu","doi":"10.1109/ESTC48849.2020.9229856","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229856","url":null,"abstract":"In this work, a graphene assembled film integrated heat sink and water cooling technology was used to build an experimental set-up of a thermal management system to demonstrate the possibility to achieve efficient cooling of the propulsion battery in electric vehicles. The experimental results showed that the temperature decrease of a Li-ion battery module can reach 11°C and 9 °C under discharge rates as of 2C and 1C, respectively. The calculated thermal resistance of the graphene based cooling system is about 76% of a similar copper based cooling system. Surface modification was carried out on the graphene sheet to achieve a reliable bonding between the graphene sheet and the battery cell surface. This work provides a proof of concept of a new highly efficient approach for electric vehicle battery thermal management using the light-weight material graphene.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"56 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84517178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}