A System Level SI-PI co-simulation of LPDDR4x at 4267Mbps Speed

Abstract

A system level SI-PI co-simulation of LPDDR4x 4267 Mbps is presented. Power Supply Induced Jitter (PSIJ) is estimated based on noise numbers of IO and core supplies. This PSIJ is fed into signal integrity simulation with ideal power to evaluate write and read margins. Layout and stackup optimization of both package and PCB is discussed in detail. Eye height and Eye width are measured and compared with Tx and Rx specification to conclude good margins.