2019 Pan Pacific Microelectronics Symposium (Pan Pacific)最新文献

{"title":"New Era of Device Science","authors":"T. Kasahara, H. Kuwae, J. Mizuno","doi":"10.23919/PANPACIFIC.2019.8696587","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696587","url":null,"abstract":"Micro and nanofabrication processes have significant impact on the recent development of semiconductor integrated circuits, micro/nano-electromechanical systems (MEMS/NEMS), biosensors, and optoelectronic devices. In addition, several semiconductor wafer bonding and two point five-dimensional (2.5D)/three-dimensional (3D) integration technologies have been proposed in order to develop advanced electronic device applications. On the other hand, organic electronic devices, which consist of organic semiconducting materials instead of traditional inorganic materials such as silicon, have attracted attention for applications in flexible devices, wearable devices, and others. In particular, organic light-emitting diodes (OLEDs) have recently reached the stage of commercialization of new light sources and flat-panel displays. Our research group have focused on studies on novel inorganic and organic electronic devices. This presentation provides a brief overview of the authors’ own recent researches on nanofabrications, homogeneous and heterogeneous bonding technologies, and functional microdevices. We especially discuss our organic electroluminescent device applications such as the nano-OLEDs and the microfluidic OLEDs.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"10 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2019-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89252867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced Package Wiring Technology Solution for Heterogeneous Integration","authors":"Y. Morikawa","doi":"10.23919/PANPACIFIC.2019.8696855","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696855","url":null,"abstract":"Smart ICT (Information and Communication Technology) such as “Big Data”, “Cloud computing” and Smart Functionalities such as}Stand-alone Self-activating MEMS/Sensors construct Smart Systems which enable IoT (Internet of Things), IoE (Internet of Everything) thus Smart Society. High-density Packaging technologies such as 3D, 2.5D packaging scheme basing on TSV (through-Si via) technology and PWB (printed wiring board) packaging as high-density interposer are among key technologies to satisfy the requirements from the both smart semiconductor devices for AI (artificial intelligence), and smart functional devices for “Edge-computing”. Meanwhile MEMS/Sensors are required as multi-functionalities of stand-alone smart devices for wearable devices including smart phone, an important part of smart-systems. Thus, the demand of high density FO-SiP (fan-out system in packaging) is growing. In order to accomplish high-density packaging as homogeneous and heterogeneous integration, miniaturization of wiring in organic package is needful to MCM (multi chip module) system fabrication on the PWB. To obtain vias in a build-up film, the laser drilling process is widely used but there are three major restricting difficulties. The first is that it is difficult to make fine vias and line / space because of laser wave length limitation. The second is that wet desmear process to remove smear for each generation’s build-up films is also will be issue by swelling and silica-residue problem. And finally, such kind of technologies cannot intentionally control of surface roughness for build-up film. In this study, a fine via and line and space patterns processing below $10 mu mathrm{m}$ with low surface-roughness in a low-CTE (coefficient of thermal expansion) Build-up film was achieved by using a plasma dry process. That technology applications are dry desmear and dry etching for fan-out wiring fabrication.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"121 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86854394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Managing 21st Century Workforce","authors":"O. Aina, K. Verma","doi":"10.23919/PANPACIFIC.2019.8696750","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696750","url":null,"abstract":"Organizations in the 21st century require managers who possess the ability to create employee satisfaction through the right leadership style. Boleslaw (2009) observed that some senior managers believe leadership is about power-holding to manipulate and control the employees. Such leadership style may cause employees’ dissatisfaction with their jobs and affect the performance of organizations operating in the competitive business environment. A quantitative correlational research study was conducted to investigate the relationship between leadership style of the senior managers and job satisfaction and commitment of the middle managers working at the corporate headquarters of a communications company in Atlanta, Georgia, USA. In the research study, 166 middle managers of the organization were involved. The middle managers implement organizational strategies, oversee departments within the organization, and report to their respective senior managers. The senior managers included the chief executive officers and the division heads who create strategies for the middle managers to implement. The independent variable examined in the quantitative correlational research study was the leadership style of the senior managers measured with the attributes of transformational, transactional, and laissez-faire leadership styles. The dependent variable was the job satisfaction of the middle managers and their commitment to the organization. The research instruments used to collect data for the current research study were the MLQ Rater Form 5X-Short to investigate leadership style, Job in General Survey (JIG) instrument to evaluate job satisfaction and Organizational Commitment Questionnaire (OCQ) to measure employee commitment to their organization. A demographic questionnaire was developed for the research study to describe the participants and analyze sub-groups of the participants. The statistical analysis SPSS Version 20.0 was used to collate data and calculate descriptive statistics such as mean, standard deviation, minimum, and maximum for each leadership style and overall job satisfaction. Descriptive statistics, Pearson correlation coefficient, the analysis of variance (ANOVA), and multiple regression analysis were used for the data analysis. Analysis of the data found that transformational leadership style has a positive correlation on employee job satisfaction and employee commitment. A higher level of job satisfaction and employee commitment for employees who had managers who exhibited transformational leadership was observed. Analysis of the demographic variables found that demographic variables moderated the relationship between leadership style of the senior managers and job satisfaction of the middle managers. The study found that employees, most especially, middle managers of communications industry preferred their senior managers to exhibit more of transformational leadership features, less of transactional leadership, and little or no of lais","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"1 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83639355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"I/O Planning and Cross-Hierarchical Optimization for Advanced Electronic “Systems 4.0”","authors":"A. Fontanelli, M. Taliercio, F. Rossi","doi":"10.23919/PANPACIFIC.2019.8696372","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696372","url":null,"abstract":"We are at the dawn of the fourth industrial revolution – also known as “Industry 4.0”, which demands for even more integrated, heterogeneous electronic systems. “Systems 4.0” are actually a prerequisite for the Industry 4.0 to happen. The ability to dramatically slash the footprint, and the power envelope of increasingly complex, highly heterogeneous electronic systems is critical, and can be achieved only through their “siliconization”, i.e. moving from board-level integration to chip-level integration – 2.5D, 3D, and 5.5.D – with multiple silicon components either stacked on top of one another, or placed side-by-side onto a silicon interposer, or hybrid combinations of the previous solutions. The “communication” – I/O – among the compute, memory, interface, sense, actuate components of Systems 4.0 is going to play a fundamental role in the feasibility itself of Systems 4.0: I/O takes a 50% toll on the total power envelope of the systems, and has become a blockage towards higher bandwidth (performance). From the electronics perspective, these developments will be enabled by a series of innovations in the design and production chain of integrated circuits. The characteristics and heterogeneity of advanced systems and also the exponential growth of the I/O number, call for the development of I/O optimization algorithms, taming the computational complexity of the 2.5D and 3D-IC designs. Also, this technology demands for a heterogeneous co-design environment, integrated with traditional Package and IC Design Tools via standard formats, in order to design with a streamline flow.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"39 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73626806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Real-time Reliability Testing Advancements on Production Electronic Hardware","authors":"M. Bixenman, Mark McMeen","doi":"10.23919/PANPACIFIC.2019.8696621","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696621","url":null,"abstract":"OEMs (Original Equipment Manufacturers) and EMSs (Electronic Manufacturing Services) work to a set of guidelines and test procedures for qualification of hardware when changing soldering materials, process conditions, cleaning materials, cleaning machines, and conformal coating. Evaluation and use of any soldering material, reflow setting, or cleaning material, the EMS shall confirm that the proposed materials are characterized and qualified to the applicable ANSI/IPC Industry Standards. Additionally, IPCJ-STD-001G, Amendment 1 issued changes to Cleanliness Standards requiring the assembler to develop objective evidence that a specific cleanliness condition renders a reliable device.For many PCB designs with complex component geometries, cleanliness can impact reliability and circuit performance. The gold standard for circuit qualification has been to pass SIR (Surface Insulation Resistance) testing with resistivity values that show that the design and process do not interfere with the circuit performance. Up until now, SIR testing hasn’t been practical on the manufacturing floor as the test traditionally takes seven days to complete, and requires equipment that is complicated to use. The purpose of this research is to design instrumentation and test methods that allow both the OEM and EMS to perform process development and process control using electrical test methods for use in an operations environment.The research study centers on “On-going Reliability Testing” that allows the assembler to take testing to the technician level. Using a combination of modern, configurable test cards that scrutinize high-risk circuits and devices integrated on the assembly, the EMS can correlate cleanliness to production hardware. This bottom-up testing methodology allows the assembler to repeat IPC testing in their factory – objective evidence to J-STD-001G, Amendment 1. Also, they can expand testing to other areas such as system design, process development, process control, and quality assurance.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"245 Pt 1 1","pages":"1-13"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87572894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability Engineering Techniques for Consumer Products","authors":"John Cooper","doi":"10.23919/PanPacific.2019.8696677","DOIUrl":"https://doi.org/10.23919/PanPacific.2019.8696677","url":null,"abstract":"Consumer products have been thought of as being low priced and unreliable. We will look at some of the best approaches to use in designing and manufacturing consumer products in regard to reliability, and how these approaches can result in improved profitability without increasing cost, and some aspects of implementing these approaches. The approaches discussed here can be adapted to the special needs of small companies and startups. The intended audience here is the reliability engineer or technical manager in a small company or startup, involved in hardware product development for the consumer market. This material is aimed at those people or companies who actively care to make their products better and are willing to consider various approaches that may be within their budget. Many of the techniques involved with making consumer products more reliable are common to reliability tools used for higher end products of any quality level or cost level. Analytical tools, such as FMEA (Failure Mode Effects Analysis), or HALT (Highly Accelerated Life Testing) are very useful for improving the reliability of consumer products. In this paper, we will look at some aspects of how consumer products differ from industrial products, and what special concerns there are with product reliability; we’ll discuss Strengths, Weaknesses, Opportunities and Threats (SWOT) and how they relate to consumer products reliability. We will discuss how reliability tools and methods for consumer products differ from higher end products, what tools are practical, and how some other aspects of consumer product quality and reliability differ. The special needs of the small company or startup will be considered, showing what reliability methods are more practical.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"142 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73377347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Hybrid Multicloud System for Effective Supply Chain Product Information Dissemination","authors":"N. Nagaraj","doi":"10.23919/PANPACIFIC.2019.8696281","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696281","url":null,"abstract":"Effective supply chain communication is of paramount importance in todays world, more so than ever. This is because of the greater disclosure, notification and safe use information dissemination needs placed on every part or article placed on the market. The fact that the extended supply chain is often more than sixteen layers deep and spanned across all continents and oceans makes it even more complex. When one considers the cross-sector supply chain and the nature and scope of materials and substances involved, one begins to see the extent of the complexity. Added to this, is the fact that in various parts of the world, the language requirements will be different. Yet, when a product is placed on the market in those areas, the regulatory regime will require that critical compositions and safe usage be posted in local languages and/or in visually understandable pictures and representations/images/videos. The underlying data that must be communicated is often of myriads of forms, including spreadsheets, structured data and also unstructured data and images and videos. It is also important to consider that supply chain data must have the following characteristics:1.It must be standards based.2.By nature, multiple language and character sets are to be allowed.3.It must be authenticatable-both provenance and the data integrity are important.4.The process for updates must allow for synchronization across the various levels of the supply chain/5.The cost burden must not be high. By its nature, supply chain data must cost as minimal as possible to promote cost effectiveness and keep overhead cost to a minimum. This is especially true for programs involving corporate responsibility (CSR) as these actions are a show of ethical behavior on the part of corporations, and thus profoundly, companies promoting ethical behavior must not be burdened with costs, as otherwise it will give the scofflaws and nonconformers of CSR an edge in business.6.Safe use data can often be in video format and thus very large in size-it may be advantageous to provide these as web links rather than attach them. It is to be noted that videos on safe use will alleviate the need for instructions to be translated into multiple languages.7.Zipping attachments is more efficient than embedding binary data in files and files could be bulky and the large files need not always be opened whereas the base file will invariably need to be read.8.Monopolistic practices should be avoided and prevented.A platform that optimizes all these needs across multiple clouds and cloud database formats was developed and best management practices reveal the advantages of such an approach.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"68 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85210717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Industry 4.0 for Advanced Inspection","authors":"R. Vaga, Keith Bryant","doi":"10.23919/PANPACIFIC.2019.8696655","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696655","url":null,"abstract":"This advanced technical solution combines the strongest in line inspection technology, which is 3D AOI with At-Line X-ray technology, giving Real Process Management.But as so often it is not so easy to turn it into reality, it requires a real commitment from different companies with differing software platforms and methods of operation. Let’s look at the issues of achieving Real Process Management; In-line X-Ray has some challenges in this environment due to False Fails and Escapes, in short if you do not have accurate data you cannot achieve improvement easily or cost effectively. So, we promote 3D AOI as a faster, more technically advanced solution, but even these systems have an Achilles Heel, they cannot inspect joints on Bottom Terminated Components (BGA’s, CSP’s, QFN’s etc.) As they have only vision and height measurement, they can measure flatness and co planarity very well, but as in line x-ray they have to make a decision based on assumptions. Or at least that was the issue until now, when a technology is available to link 3D in-line AOI to At-Line X-Ray, allowing a decision to be made based on information from both systems, indeed SPI results and Pre-Reflow AOI results can also be considered.The technology works like this: any height measurement of a BTC which the in-line 3D AOI “fails” is relayed to the At-Line X-ray and evaluated by its operator using all the technology at his disposal including ICT which gives a detailed view of all hidden joint interfaces.The results and images are then fed to a Management Information System where a technician can review the SPI data, the 3D AOI data and the x-ray results, in real time on the same monitor. He can now use his judgment to accept or fail the board, can review historic data trends to fine-tune the AOI height limits and continuously improve the process by Intelligent Feedback. The use of a brain to filter the algorithms and images to ensure maximized yields, reduced rework and lower costs. This data can then be archived and shared with other lines, other factories or even with customers.Reports can be made available to senior managers and customers showing the results of this Process Management, which is improved yields and reduced rework. In short, a process fully under control and utilizing the application of knowledge, tools and systems to measure, control, report and improve processes with the goal to meet the customer requirements profitably.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"60 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82035696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Selection and Qualification of a Local Rework Supplier","authors":"Phillip Isaacs, Mauricio Castro Gomez, Luis Kosonoy","doi":"10.23919/PANPACIFIC.2019.8696414","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696414","url":null,"abstract":"In the electronics industry there is a drive to reduce the total cost of manufacturing, while maintaining the quality and reliability of the product. The drive for lower cost can have unanticipated consequences. One such consequence is that the Electronic Manufacturing Service (EMS) provider of the Printed Circuit Board Assembly (PCBA) and the System Assembly operations aren’t collocated. In fact, often they are in different countries and on different continents. In normal operation, the supply chain implications can be managed. However, when there are reasons to modify or repair the assembly, the distance between the EMS supplier and the System Assembly location can cause major disruption and expense.There are several factors which may cause undue disruption to the supply chain. For example:1.The PCBA’s are damaged while in route to the system assembly line.2.There is a product engineering change.3.The customer order has changed and the product needs to be reconfigured.4.There are manufacturing defects which were found during inspection or system test.Whatever the cause, sending the assemblies back to their original plant of manufacture can take too much time and may require costly premium transportation to mitigate the extra time for transportation not accounted for in the product schedule.It is for these reasons and more that the process was initiated to find a local supplier skilled in the art of mechanical and solder related reworks. The ultimate rework objective is to find a Rework Supplier who can rework the product achieving the same or high quality and reliability. This report will cover in more detail the motivation to establish a local rework supplier, the selection criteria and the qualification process.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"14 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75145611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Conductive Adhesive Films (ACFs and NCFs) Materials For Electronics Packaging Applications","authors":"K. Paik","doi":"10.23919/PANPACIFIC.2019.8696878","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696878","url":null,"abstract":"Due to the increasing demand for higher performance, greater flexibility, smaller size, and lighter weight in mobile and wearable electronic products, there have been growing needs of various electronic packaging products and fine-pitch interconnection technologies. To realize various state-of-art mobile and wearable electronic products, fine pitch and flexible packaging & interconnection technologies are needed. As one of the promising fine pitch and flexible packaging and interconnection technologies, conductive adhesive films materials such as ACFs(Anisotropic Conductive Films) and NCFs(Non Conductive Films) are widely used now.In general, ACFs have two technical limitations such as (1) ultra-fine pitch shortage free interconnection and (2) higher current handling capability. For (1) ultra-fine pitch applications without electrical shortage, new concept of Nano-fiber ACFs and APL(Anchoring Polymer Layer) ACFs have been successfully invented by KAIST both for less than 20 micron pitch COG(Chip On Glass), COP(Chip On Polymer). and COF(Chip On Flex). And they can be also used for less than 50 micron pitch FOF(Flex On Flex) and FOB(Flex On Board) applications. In addition, for (2) higher current handling capability applications, new solder ACFs have been also introduced by KAIST to replace the conventional metal particles based ACFs interconnection. By solder ACFs, 30% low contact resistance, 4 X higher current handling capability, and excellent reliability were successfully achieved compared with conventional ACFs. Furthermore, ACFs materials-based packaging and interconnection method can provide the flexible interconnect solution for OLED(Organic LED) COP and COF/CIF(Chip In Flex) packages to realize wearable electronic products.Recently the 3-D die chip stacking using the Through silicon via (TSV) technology has been widely used for stacking memory and ASIC chips. In the 3D-TSV vertical interconnection, Cu pillar/Sn-Ag eutectic solder bump is one of the promising bonding method. After the 3D-TSV chips are interconnected with the bumps, the gap between stacked chips should be filled with underfill materials. However, capillary flow underfill between 3D-TSV stacked chips become difficult because of increased chip/wafer area, decreased gap height, and multiple chip/wafer stacking. Therefore, new bonding method using NCFs materials, which performs both Cu-pillar/Sn-Ag flip chip bump to metal pads interconnection and underfils at the same time has been extensively used.In this presentation, the ACFs materials for ultra-fine pitch and higher current carrying interconnection and the NCFs for 3D-TSV chip stacking applications will be introduced.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"15 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86578255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}