2019 Pan Pacific Microelectronics Symposium (Pan Pacific)最新文献

{"title":"Moore’s Law for Packaging to Replace Moore’s Law for ICS","authors":"R. Tummala","doi":"10.23919/PANPACIFIC.2019.8696409","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696409","url":null,"abstract":"This article proposes Moore’s Law for Packaging to replace Moore’s Law for ICs, as this is seen as coming to an end. Moore’s Law for ICs is about scaling transistors to ever smaller sizes, from node to node and interconnecting and integrating these to result in more transistors in smaller chips at lower cost from 300 mm wafers. As transistor scaling and integration comes to an end due to physical, material and electrical limitations, Moore’s Law for Packaging (MLP) can be viewed as interconnecting and integrating smaller chips with the highest transistor density with the highest performance at the lowest cost. Package or system scaling is proposed to be one and the same as the end goal of packaging is a system. Just as Moore’s Law has two components: number of transistors and cost of each transistor, Moore’s Law for Packaging is proposed to have two components as well: the number of interconnections or I/Os and the cost of each I/O. This article lays the ground work for Moore’s Law for Packaging by showing how I/Os have evolved from one package family node to the next, starting with <16 I/Os in 1960s to the current silicon interposers with about 200,000 I/Os. It proposes a variety of ways to extend Moore’s Law such as extending Si interposers and beyond, using glass in panel embedding. As Moore’s Law for Electronic Packaging comes to its own end, this article proposes 3D opto-electronic packaging as the next Moore’s Law for Packaging.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"340 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77660895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tin Whiskers 101: 2019","authors":"Ronald C. Lasky, A. Balch","doi":"10.23919/PANPACIFIC.2019.8696615","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696615","url":null,"abstract":"Tin whiskers continue to be a major concern in electronics assembly. This paper will firstly give an explanation of tin whiskers and their formation. Secondly, it will summarize their potential risks and mitigation techniques. A description of Failure Modes and Effects Analysis (FMEA) as a technique to assess tin whisker risk, for a given technology, will be then be discussed.This paper will conclude with a discussion of tin whisker reliability strategies for consumer and mission critical products. At the end of the presentation, attendees will have all of the basic relevant information to develop an effective tin whisker strategy.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"135 1","pages":"1-14"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74582232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal Scanning Probe Lithography (t-SPL) for Nano-Fabrication","authors":"H. Wolf, Y. Cho, S. Karg, P. Mensch, C. Schwemmer, A. Knoll, M. Spieser, Samuel Bisig, C. Rawlings, P. Paul, F. Holzner, U. Duerig","doi":"10.23919/PANPACIFIC.2019.8696898","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696898","url":null,"abstract":"Thermal scanning probe lithography (t-SPL) is a direct-write patterning method that creates high-resolution features with a heated scanning probe tip in an organic resist material. It is able to produce dense high-resolution patterns with sub-20 nm half-pitch at ambient conditions which can be transferred into silicon substrates using a hard-mask patterning stack and reactive ion etching (RIE). Feature sizes of transferred lines can be as small as 7 nm. Linear write speeds of up to 20 mm/s can be achieved. Different from e-beam lithography (EBL), in t-SPL proximity effects are absent and substrate damage of sensitive materials caused by high energy electrons is avoided. A direct inspection of the patterned area is provided during the writing process. Overlay patterning without additional alignment marks onto pre-existing structures is another feature of the t-SPL method. Existing device structures can be located precisely under a resist stack with the local probe tip and the additional target structures can then be generated with $lt 5$ nm-precise overlay alignment. One further strength of tSPL is the capability of producing 3D patterns. The process can be controlled to produce 3D structures with $approx 1$ nm $(1 sigma)$ depth accuracy. Examples of unique devices fabricated by tSPL will be discussed.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"15 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81515110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Practical way to Limit Counterfeits","authors":"Cameron E. Shearon","doi":"10.23919/PanPacific.2019.8696277","DOIUrl":"https://doi.org/10.23919/PanPacific.2019.8696277","url":null,"abstract":"The traditional methods of addressing the risk of counterfeits have been viewed as purely a cost to the business that was better than the alternatives. Historically, the risks of counterfeits using traditional methods have been reasonably sufficiently addressed by traditional Quality, Supply Chain Management, better labeling & packaging, statistical sampling, and security measures, as well as, analytical techniques such as Real Time X-Ray, various forms of microscopy, and chemical analysis. As counterfeiters have accumulated more resources, they have been able to rapidly find increasingly more sophisticated methods around the relatively static methods of preventing and finding counterfeits. The effectiveness of the methods traditionally used to mitigate the risk of counterfeits such as security guards, locked containers, using known suppliers, etc. have been less than 100% effective and very costly to implement and maintain. This paper outlines a more modern method of enhancing the traditional analytical techniques, and creates a value-added method that by blending existing tools for Quality, Reliability, Product Safety, Regulatory, Product Development, Marketing, Leadership, and Operations, works more productively, with less effort. The methodology shown in IPC-1782 can be applied to products outside of the Electronics Industry including, but not limited to, medical devices, automobiles, food, appliances, etc. Because these are off-the-shelf solutions, they are relatively easily implemented and provide unprecedented controls and productivity gains over every part of a business. Variability causes quality, reliability (quality over time), and product safety issue. Interchangeable parts enabled the industrial revolution because they addressed variability. What gets measured tends to get managed. This combination of tools enables a tailorable solution that is proportionate to the need and available resources. This combination of tools also enables a reduction in variability that is on the same order of magnitude as interchangeable parts. Therefore, this solution fits very well with Industry 4.0 and can be utilized to create entirely new business models, as well as, a practical way to address the risk of counterfeits for a very long time.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"6 4","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91489616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"What Does My Shirt Tell Me? The Integrating of Electronics in Clothing","authors":"K. Jansen","doi":"10.23919/PANPACIFIC.2019.8696601","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696601","url":null,"abstract":"The era of smart textiles has begun. Sensors become smaller, more reliable and require less power and the market of garments for health monitoring increases exponentially. The challenges still are in the seamless integration, robustness and ease of use. In this paper the developments and trends are discussed.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"37 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82012095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CU Paste for Molded Interconnect Devices","authors":"Y. Ejiri, Shinichirou Sukata, Masaya Toba, K. Urashima, M. Yonekura, Takaaki Noudou, Y. Kurihara, H. Masuda","doi":"10.23919/PANPACIFIC.2019.8696671","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696671","url":null,"abstract":"Cu particles with an average particle size of 130 nm were found to be suitable for low-temperature metallization. Cu wirings with line/space $(L/S) = 150~mu m/ 150~mu m$ and $L/S= 150~mu m/100~mu m$ were formed by screen printing and aerosol jet printing, respectively. The shear strength of the Cu wiring that was covered by the SnBi solder including epoxy resin and liquid-crystalline polymer substrate was 7 MPa; the shear strength was maintained even after a high-temperature storage test (125 °C for 200 h). The developed Cu paste could be used as a via connection material, and employed for the fabrication of Cu wiring on two-dimensional and three-dimensional substrates.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"150 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81721746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Pan Pacific 2019 Copyright Page","authors":"","doi":"10.23919/panpacific.2019.8696763","DOIUrl":"https://doi.org/10.23919/panpacific.2019.8696763","url":null,"abstract":"","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"11 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76244119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New-Automotive -Autonomous Driving Challenges For The Microelectronic Components","authors":"K. Weide-Zaage","doi":"10.23919/PANPACIFIC.2019.8696273","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696273","url":null,"abstract":"Key focus of the European Research in Horizon 2020 is ‘digital transformation’. This means the strategic and disruptive evolution towards a digital society. The connection between IoT (Internet of Things), big data and AI (artificial intelligence) and autonomous systems like robotic, automation, machine learning and self-driving impact the innovation in products, processes and business models. Generally, many subjects and challenges have to be addressed in this frame. This are safety, security, privacy, sensors and actuators, the development of software within the scope of life cycle issues, system integration, connected vehicles, vehicle sensors with external sources (V2X also called CAR2X), standardization, situation understanding, cognition and decision-making. Furthermore, insurances as well as the General Data Protection Regulation (GDPR) will influence the field of autonomous driving.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"18 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87024231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TRIZ-Based Design of an LCD for Projectors","authors":"Y. Takafuji","doi":"10.23919/PanPacific.2019.8696808","DOIUrl":"https://doi.org/10.23919/PanPacific.2019.8696808","url":null,"abstract":"TRIZ, Russian acronym for \"Theory of Inventive Problem Solving\" is now becoming well known and being applied to the various engineering field in the Western and Asian countries. However, as only few successful examples on the problems in microelectronics are found in the literature. Therefore, the previous work on a small high resolution TFT-LCD (Thin Film Transistor Addressed Liquid Crystal Display) for projection display was investigated and analyzed from TRIZ point of view to see its usefulness to solve engineering problems in the microelectronics field.There was a conflict between existence of spacers necessary to keep cell gap of LCD (Liquid crystal Display) uniform, which is related to the transmission uniformity of the screen, and serious degradation of image quality due to existence of spacers, which are recognized as a bright spot on the dark screen, as the spacer size compared with pixel size becomes large. The problem was analyzed by the TRIZ framework, and the solution to the above conflict in manufacturing an LCD for projection display was found systematically by utilizing TRIZ framework.Also, further problem of conflicting features between “productivity” and “manufacturing precision” and several other issues in production of small TFT-LCD for projection displays are studied by using TRIZ framework, and get to a new device structure and fabrication process as a FIR (Final Ideal Result). In this approach, TFT array formed on the Si wafer is transferred onto the other substrate such as glass with high strain-point, Eagle XG, and AN100, etc. used in the TFT-LCD industry. The hydrogen exfoliation technique and fragile layer are exploited to transfer device layers to the other substrates. In the present proposal, TFTs are perfect single crystal, in contrast to the poly-Si TFT used in the current LCDs, and this eliminates issue of characteristics variation stemming from the grain boundary of Poly-Si.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"87 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86569901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact Of Stencil Quality & Technolgy On Solder Paste Printing Performance","authors":"Jeffrey Len Yung Kwuan, L. Rao, Evan Yip, Wisdom Qu, J. Sjoberg","doi":"10.23919/PANPACIFIC.2019.8696551","DOIUrl":"https://doi.org/10.23919/PANPACIFIC.2019.8696551","url":null,"abstract":"The growth of the Internet of Things (IoT) has greatly increased miniaturization development in packaging and board level assembly. As the industry is moving to smaller and finer pitches such as 008004, 0.3mm CSP, and BGA, screen printing becomes one of the critical processes to produce a good quality surface mount assembly. It has been widely accepted that 50–70% of SMT defects come from printing applications. There are many variables that will affect the quality of printing such as machine set up, solder paste handling and storage, stencil quality, stencil aperture design, printing parameters, and others. In this paper, we will evaluate the impact of stencil quality statistically through MiniTab software by comparing the printing performance of 0.35mm pitch and 01005 pads from different stencil suppliers.","PeriodicalId":6747,"journal":{"name":"2019 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"41 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80562783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}