I/O Planning and Cross-Hierarchical Optimization for Advanced Electronic “Systems 4.0”

Abstract

We are at the dawn of the fourth industrial revolution – also known as “Industry 4.0”, which demands for even more integrated, heterogeneous electronic systems. “Systems 4.0” are actually a prerequisite for the Industry 4.0 to happen. The ability to dramatically slash the footprint, and the power envelope of increasingly complex, highly heterogeneous electronic systems is critical, and can be achieved only through their “siliconization”, i.e. moving from board-level integration to chip-level integration – 2.5D, 3D, and 5.5.D – with multiple silicon components either stacked on top of one another, or placed side-by-side onto a silicon interposer, or hybrid combinations of the previous solutions. The “communication” – I/O – among the compute, memory, interface, sense, actuate components of Systems 4.0 is going to play a fundamental role in the feasibility itself of Systems 4.0: I/O takes a 50% toll on the total power envelope of the systems, and has become a blockage towards higher bandwidth (performance). From the electronics perspective, these developments will be enabled by a series of innovations in the design and production chain of integrated circuits. The characteristics and heterogeneity of advanced systems and also the exponential growth of the I/O number, call for the development of I/O optimization algorithms, taming the computational complexity of the 2.5D and 3D-IC designs. Also, this technology demands for a heterogeneous co-design environment, integrated with traditional Package and IC Design Tools via standard formats, in order to design with a streamline flow.