异构集成的先进封装布线技术解决方案

Y. Morikawa
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引用次数: 1

摘要

“大数据”、“云计算”等智能ICT(信息通信技术)和独立自激活MEMS/传感器等智能功能构建了智能系统,使IoT(物联网)、IoE(万物互联)成为智能社会。高密度封装技术,如基于TSV (through-Si via)技术的3D、2.5D封装方案和作为高密度中间层的PWB (printed wiring board)封装,是满足AI(人工智能)智能半导体器件和“边缘计算”智能功能器件需求的关键技术之一。同时,包括智能手机在内的可穿戴设备作为智能系统的重要组成部分,需要MEMS/传感器作为单机智能设备的多功能。因此,对高密度FO-SiP(封装中的扇出系统)的需求正在增长。为了实现均匀集成和异构集成的高密度封装,在pcb上制造MCM(多芯片模块)系统需要实现有机封装中布线的小型化。为了在堆积膜中获得通孔,激光打孔工艺得到了广泛的应用,但存在三个主要的限制困难。首先,由于激光波长的限制,难以制作精细的通孔和线/空间。其次是湿式除污工艺,对于每一代的涂膜堆积也是会出现膨胀和硅渣问题的。最后,这种技术不能有意地控制堆积膜的表面粗糙度。在这项研究中,通过使用等离子体干燥工艺,在低cte(热膨胀系数)堆积膜中实现了低于$10 \mu \ mathm {m}$的精细通孔、线和空间图案加工,表面粗糙度低。该技术应用于扇形布线的干涂和干蚀刻。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Advanced Package Wiring Technology Solution for Heterogeneous Integration
Smart ICT (Information and Communication Technology) such as “Big Data”, “Cloud computing” and Smart Functionalities such as}Stand-alone Self-activating MEMS/Sensors construct Smart Systems which enable IoT (Internet of Things), IoE (Internet of Everything) thus Smart Society. High-density Packaging technologies such as 3D, 2.5D packaging scheme basing on TSV (through-Si via) technology and PWB (printed wiring board) packaging as high-density interposer are among key technologies to satisfy the requirements from the both smart semiconductor devices for AI (artificial intelligence), and smart functional devices for “Edge-computing”. Meanwhile MEMS/Sensors are required as multi-functionalities of stand-alone smart devices for wearable devices including smart phone, an important part of smart-systems. Thus, the demand of high density FO-SiP (fan-out system in packaging) is growing. In order to accomplish high-density packaging as homogeneous and heterogeneous integration, miniaturization of wiring in organic package is needful to MCM (multi chip module) system fabrication on the PWB. To obtain vias in a build-up film, the laser drilling process is widely used but there are three major restricting difficulties. The first is that it is difficult to make fine vias and line / space because of laser wave length limitation. The second is that wet desmear process to remove smear for each generation’s build-up films is also will be issue by swelling and silica-residue problem. And finally, such kind of technologies cannot intentionally control of surface roughness for build-up film. In this study, a fine via and line and space patterns processing below $10 \mu \mathrm{m}$ with low surface-roughness in a low-CTE (coefficient of thermal expansion) Build-up film was achieved by using a plasma dry process. That technology applications are dry desmear and dry etching for fan-out wiring fabrication.
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