2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第6页

Adaptive Transceiver for Wireless NoC to Enhance Multicast/Unicast Communication Scenarios 无线NoC自适应收发器增强多播/单播通信场景

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00111

Joel Ortiz Sosa, O. Sentieys, C. Roland

引用次数: 6

Micro-electrode-dot Array Based Biochips : Advantages of Using Different Shaped CMAs 基于微电极点阵列的生物芯片:使用不同形状cma的优势

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00061

Pampa Howladar, P. Roy, H. Rahaman

{"title":"Micro-electrode-dot Array Based Biochips : Advantages of Using Different Shaped CMAs","authors":"Pampa Howladar, P. Roy, H. Rahaman","doi":"10.1109/ISVLSI.2019.00061","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00061","url":null,"abstract":"Recent emergence of micro-electrode-dot array (MEDA) based digital microfluidic biochips has facilitated major improvement in microfluidic operations for conventional lab-on-chip devices. MEDA based digital microfluidic biochips typically consist of a 2D planar array of cells of square sized microelectrodes. One of the most critical issues in the biochip layout design is the droplet transportation within the 2D layout. MEDA allows for dynamic routing with variable shaped and sized droplets. Microelectrode cells are dynamically group together to form configured microelectrode array (CMA) for variable shaped and sized droplets. This existing square shaped CMA is highly suitable for the droplets that needs exactly rectangular or square area but may not be as effective for rhombus or hexagonal shaped areas occupied by droplets. This is because the occupied additional area may be useful for other droplets to accommodate their corresponding minimum shortest path. In this paper, we present some MEDA layout design of 2D planar array of cells using triangle shaped microelectrodes by arranging them in a regular way. This allows for better convenience towards formation of different droplet shapes more efficiently, specifically for rhombus or hexagonal sized droplets. MEDA routing operations has been conducted on this newly proposed MEDA layout (using variable shaped electrodes) followed by analysis and comparison with existing MEDA layout design. Finally droplet transportation with standard bench marks are mapped in order to demonstrate how well the proposed designs can improve the performance of bioassay execution in MEDA based DMFB layout.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"180 1","pages":"296-301"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85190324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Message from the Technical Program Chairs 来自技术项目主席的信息

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/SCORED.2010.5703958

M. Ismail, Zaini Jamaludin

引用次数: 0

SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage 近阈值电压下高效节能存储器的SRAM片上监测方法

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00035

Taehwan Kim, Kwangok Jeong, Taewhan Kim, Kyumyung Choi

{"title":"SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage","authors":"Taehwan Kim, Kwangok Jeong, Taewhan Kim, Kyumyung Choi","doi":"10.1109/ISVLSI.2019.00035","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00035","url":null,"abstract":"Low power design by near-threshold voltage (NTV) operation is very attractive since it affords to considerably mitigate the sharp increase of power dissipation. However, one key barrier for the use of NTV operation is the significant increase of the SRAM failure. In this work, we propose an on-chip SRAM monitoring methodology that is able to accurately predict the minimum voltage, Vddmin, on each die that does not cause SRAM failure under a target confidence level. Precisely, we propose an SRAM monitor, from which we measure a maximum voltage, Vfail that causes functional failure on that SRAM monitor. Then, we propose a novel methodology of inferring SRAM Vddmin on each die from the measured Vfail of SRAM monitor on the same die where Vfail-Vddmin correlation table is built-up in design infra development phase, and Vddmin can be directly derived from the measured Vfail referencing the correlation table in silicon production phase. Through experiments, we confirm that our proposed methodology is able to save leakage power by 7.43%, read energy by 3.98%, and write energy by 4.06% in SRAM bitcell array over that by applying a uniform minimum voltage for all dies while meeting the same yield constraint.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"27 1","pages":"146-151"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82511491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Impact of Autocorrelation on Stochastic Circuit Accuracy 自相关对随机电路精度的影响

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00057

T. Baker, J. Hayes

引用次数: 3

Persistently-Secure Processors: Challenges and Opportunities for Securing Non-Volatile Memories 持久安全处理器:保护非易失性存储器的挑战和机遇

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00114

Amro Awad, S. Suboh, Mao Ye, Kazi Abu Zubair, Mazen Al-Wadi

引用次数: 12

T-DLA: An Open-source Deep Learning Accelerator for Ternarized DNN Models on Embedded FPGA

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00012

Yao Chen, Kaili Zhang, Cheng Gong, Cong Hao, Xiaofan Zhang, Tao Li, Deming Chen

{"title":"T-DLA: An Open-source Deep Learning Accelerator for Ternarized DNN Models on Embedded FPGA","authors":"Yao Chen, Kaili Zhang, Cheng Gong, Cong Hao, Xiaofan Zhang, Tao Li, Deming Chen","doi":"10.1109/ISVLSI.2019.00012","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00012","url":null,"abstract":"Deep Neural Networks (DNNs) have become promising solutions for data analysis especially for raw data processing from sensors. However, using DNN-based approaches can easily introduce huge demands of computation and memory consumption, which may not be feasible for direct deployment onto the Internet of Thing (IoT) devices, since they have strict constraints on hardware resources, power budgets, response latency, and manufacturing cost. To bring DNNs into IoT devices, embedded FPGA can be one of the most suitable candidates by providing better energy efficiency than GPU and CPU based solutions, and higher flexibility than ASICs. In this paper, we propose a systematic solution to deploy DNNs on embedded FPGAs, which includes a ternarized hardware Deep Learning Accelerator (T-DLA), and a framework for ternary neural network (TNN) training. T-DLA is a highly optimized hardware unit in FPGA specializing in accelerating the TNNs, while the proposed framework can significantly compress the DNN parameters down to two bits with little accuracy drop. Results show that our training framework can compress the DNN up to 14.14x while maintaining nearly the same accuracy compared to the floating point version. By illustrating our proposed design techniques, the T-DLA can deliver up to 0.4TOPS with 2.576W power consumption, showing 873.6x and 5.1x higher energy efficiency (fps/W) on ImageNet with Resnet-18 model comparing to Xeon E5-2630 CPU and Nvidia 1080 Ti GPU. To the best of our knowledge, this is the first instruction-based highly efficient ternary DLA design reported from the literature.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"13-18"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81635472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Deep State Encryption for Sequential Logic Circuits 顺序逻辑电路的深度状态加密

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00068

Yasaswy Kasarabada, Sudheer Ram Thulasi Raman, R. Vemuri

引用次数: 7

In-memory AES Implementation for Emerging Non-Volatile Main Memory 新兴非易失性主存储器的内存AES实现

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00027

Mimi Xie, Yawen Wu, Zhenge Jia, J. Hu

{"title":"In-memory AES Implementation for Emerging Non-Volatile Main Memory","authors":"Mimi Xie, Yawen Wu, Zhenge Jia, J. Hu","doi":"10.1109/ISVLSI.2019.00027","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00027","url":null,"abstract":"Non-volatile memories are very promising candidates to be employed as next-generation non-volatile main memory (NVMM), because of their advantages over traditional DRAM main memory such as non-volatility, high density, and low leakage power. However, NVMM suffers a new security vulnerability because the nature of non-volatility allows the data to be retained a long time after power is off. An attacker with physical access to the system can readily scan the main memory content and extract all valuable information from the main memory. To protect the data of the NVMM, the whole memory should be provided with a security mechanism with comparable security level to DRAM. Take mobile devices (e.g. smart phone or laptop) for example, once attackers have physical access to the NVMM will they be able to read out the sensitive information. Therefore, memory encryption is required only when the device is shut down or put into sleep/screenlock mode. One-time encryption, encrypting the whole/most part of the memory only when it is necessary, is an efficient solution in such mobile scenarios. However, one-time memory encryption approach faces two challenges: First, it should be fast enough to maintain a low vulnerability window when locked and provide instant response when unlocked. Second, it should be energy-efficient considering the limited battery life.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"56 1","pages":"103-103"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81569196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design of Switched-Current Based Low-Power PIM Vision System for IoT Applications 基于开关电流的物联网低功耗PIM视觉系统设计

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00041

Zheyu Liu, Zichen Fan, Qi Wei, Xing Wu, F. Qiao, Ping Jin, Xinjun Liu, Chengliang Liu, Huazhong Yang

引用次数: 1