2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第5页

Design of Quantum Circuits for Cryptanalysis and Image Processing Applications 用于密码分析和图像处理应用的量子电路设计

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00072

Edgard Muñoz-Coreas, H. Thapliyal

{"title":"Design of Quantum Circuits for Cryptanalysis and Image Processing Applications","authors":"Edgard Muñoz-Coreas, H. Thapliyal","doi":"10.1109/ISVLSI.2019.00072","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00072","url":null,"abstract":"Quantum circuits for arithmetic functions over Galois fields such as squaring are required to implement quantum cryptanalysis algorithms. Quantum circuits for integer arithmetic such as multiplication are required to implement scientific computing algorithms and quantum image processing algorithms on quantum computers. Reliable quantum circuits require error correcting codes and gates that are fault tolerant in nature. Quantum circuits of many qubits are challenging to implement making designs with low qubit cost desirable. In this work, we present quantum arithmetic circuits for applications in quantum cryptanalysis and quantum image processing. We present a proposed algorithm for synthesizing gate cost, qubit cost and depth optimized Galois field (GF(2^m)) squaring circuits for quantum cryptanalysis applications. In addition, these squaring circuits are incorporated into a proposed quantum circuit for inversion in GF(2^m). This work also presents a proposed quantum integer conditional addition circuit and a quantum integer multiplication circuit optimized for T-count and qubit cost. The quantum conditional addition circuit and quantum multiplier are incorporated into proposed quantum circuits for bilinear interpolation optimized for T-count cost that can be used in quantum image processing applications.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"94 1","pages":"360-365"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79606804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Formal Hardware Verification of InfoSec Primitives 信息安全原语的正式硬件验证

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00034

M. Basiri, S. Shukla

引用次数: 0

FAST: A Frequency-Aware Skewed Merkle Tree for FPGA-Secured Embedded Systems FAST:用于fpga安全嵌入式系统的频率感知倾斜默克尔树

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00066

Yu Zou, Mingjie Lin

{"title":"FAST: A Frequency-Aware Skewed Merkle Tree for FPGA-Secured Embedded Systems","authors":"Yu Zou, Mingjie Lin","doi":"10.1109/ISVLSI.2019.00066","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00066","url":null,"abstract":"Protection of external memory is important when an attacker could get physical accesses to the external memory bus. Compared to general-purpose systems, embedded systems are more vulnerable to physical attacks due to the portability. One of the attacks is a replay attack, which an attacker records data sent over a memory bus and replays it to pretend to be an authorized user. Traditionally, the replay attack is protected using a full, balanced Merkle Tree. Focusing on average-case performance and general-purpose systems, traversal and verification of Merkle Tree incur a huge latency overhead to each memory access. In contrast to general-purpose systems, embedded systems are normally application-specific, and program behaviors and memory access patterns are deterministic. Besides that, we also observed that not all memory locations are accessed equally frequently given a program. Based on these two observations, we propose FAST, a Frequency-Aware Skewed merkle Tree for application-specific embedded systems. After profiling a program in a simulation environment without involving any replay attack protection, we get a memory access frequency distribution. Afterward, we design an automatic and systematic approach to generate an application-specific optimal skewed Merkle Tree accordingly. We propose an efficient hardware architecture to accelerate FAST on FPGA, and by experimenting on five real-world benchmarks, our skewed Merkle Tree implementation outperforms baseline which uses a full balanced Merkle Tree by up to 3 times.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"75 1","pages":"326-331"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85895988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Title Page i 第1页

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/isvlsi.2019.00001

引用次数: 0

A Reconfigurable Layered-Based Bio-Inspired Smart Image Sensor 一种可重构分层生物智能图像传感器

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00039

Pankaj Bhowmik, Md Jubaer Hossain Pantho, S. Saha, C. Bobda

引用次数: 0

Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm 解决基于拉格朗日松弛的离散门尺寸算法的缺陷

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00059

Henrique Placido, R. Reis

引用次数: 0

Mitigating Reverse Engineering Attacks on Deep Neural Networks 减轻对深度神经网络的逆向工程攻击

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00122

Yuntao Liu, D. Dachman-Soled, Ankur Srivastava

引用次数: 16

CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity 基于聚类稀疏性的记忆神经形态电路区域高效低功耗非原位训练框架

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00090

A. Fayyazi, Souvik Kundu, Shahin Nazarian, P. Beerel, Massoud Pedram

{"title":"CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity","authors":"A. Fayyazi, Souvik Kundu, Shahin Nazarian, P. Beerel, Massoud Pedram","doi":"10.1109/ISVLSI.2019.00090","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00090","url":null,"abstract":"Artificial Neural Networks (ANNs) play a key role in many machine learning (ML) applications but poses arduous challenges in terms of storage and computation of network parameters. Memristive crossbar arrays (MCAs) are capable of both computation and storage, making them promising for in-memory computing enabled neural network accelerators. At the same time, the presence of a significant amount of zero weights in ANNs has motivated research in a variety of parameter reduction techniques. However, for crossbar based architectures, the study of efficient methods to take advantage of network sparsity is still in the early stage. This paper presents CSrram, an efficient ex-situ training framework for hybrid CMOS-memristive neuromorphic circuits. CSrram includes a pre-defined block diagonal clustered (BDC) sparsity algorithm to significantly reduce area and power consumption. The proposed framework is verified on a wide range of datasets including MNIST handwritten recognition, fashion MNIST, breast cancer prediction (BCW), IRIS, and mobile health monitoring. Compared to state of the art fully connected memristive neuromorphic circuits, our CSrram with only 25% density of weights in the first junction, provides a power and area efficiency of 1.5x and 2.6x (averaged over five datasets), respectively, without any significant test accuracy loss.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"250 1","pages":"465-470"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75758584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

An ESL Environment for Modeling Electrical Interconnect Faults 电气互连故障建模的ESL环境

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00024

Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Z. Navabi

引用次数: 3

Computationally Efficient Learning of Quality Controlled Word Embeddings for Natural Language Processing 自然语言处理中质量控制词嵌入的计算效率学习

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00033

M. Alawad, G. Tourassi

{"title":"Computationally Efficient Learning of Quality Controlled Word Embeddings for Natural Language Processing","authors":"M. Alawad, G. Tourassi","doi":"10.1109/ISVLSI.2019.00033","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00033","url":null,"abstract":"Deep learning (DL) has been used for many natural language processing (NLP) tasks due to its superior performance as compared to traditional machine learning approaches. In DL models for NLP, words are represented using word embeddings, which capture both semantic and syntactic information in text. However, 90-95% of the DL trainable parameters are associated with the word embeddings, resulting in a large storage or memory footprint. Therefore, reducing the number of word embedding parameters is critical, especially with the increase of vocabulary size. In this work, we propose a novel approximate word embeddings approach for convolutional neural networks (CNNs) used for text classification tasks. The proposed approach significantly reduces the number of model trainable parameters without noticeably sacrificing in computing performance accuracy. Compared to other techniques, our proposed word embeddings technique does not require modifications to the DL model architecture. We evaluate the performance of the the proposed word embeddings on three classification tasks using two datasets, composed of Yelp and Amazon reviews. The results show that the proposed method can reduce the number of word embeddings parameters by 98% and 99% for the Yelp and Amazon datasets respectively, with no drop in computing accuracy.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"9 1","pages":"134-139"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72712078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2