Formal Hardware Verification of InfoSec Primitives

Abstract

Information Security (InfoSec) plays a major role in the modern real time applications. This paper proposes equivalence check based efficient formal hardware verification schemes for various InfoSec primitives such as 128-bit Advanced Encryption Scheme (AES), Bose-Chaudhuri-Hocquenghem (BCH) encoder, and m-bit GF(p) exponentiator (where p = log2m). The verification of 128-bit AES is done with Artix-7 FPGA using Xilinx Vivado. The verification of BCH encoder and GF(p) exponentiator are done with 45nm CMOS technology using Cadence. The synthesis results show that the proposed hardwaresoftware co-design based 128-bit AES formal hardware verification does not compromise the resource utilization as compared with various existing designs. Similarly, the proposed formal hardware verification of BCH encoder with generator polynomial length 64 and 16-bit GF(p) exponentiator do not compromise the delay as compared with various existing techniques.