2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第3页

Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies 忽略时钟限制:场耦合纳米技术的另一种物理设计方法

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00121

R. Wille, Marcel Walter, F. Sill, Daniel Große, R. Drechsler

{"title":"Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies","authors":"R. Wille, Marcel Walter, F. Sill, Daniel Große, R. Drechsler","doi":"10.1109/ISVLSI.2019.00121","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00121","url":null,"abstract":"Field-Coupled Nanocomputing (FCN) allows for conducting computations with a power consumption that is magnitudes below current CMOS technologies. Recent physical implementations confirmed these prospects and put pressure on the Electronic Design Automation (EDA) community to develop physical design methods comparable to those available for conventional circuits. While the major design task boils down to a place and route problem, certain characteristics of FCN circuits introduce further challenges in terms of dedicated clock arrangements which lead to rather cumbersome clocking constraints. Thus far, those constraints have been addressed in a rather unsatisfactory fashion only. In this work, we propose a physical design methodology which tackles this problem by simply ignoring the clocking constraints and using adjusted conventional place and route algorithms. In order to deal with the resulting ramifications, a dedicated synchronization element is introduced. Results extracted from a physics simulator confirm the feasibility of the approach. A proof of concept implementation illustrates that ignoring clocking constraints indeed allows for a promising alternative direction for FCN design that overcomes the obstacles preventing the development of efficient solutions thus far.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"129 1","pages":"651-656"},"PeriodicalIF":0.0,"publicationDate":"2019-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85616464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Evaluation of Compilers Effects on OpenMP Soft Error Resiliency 评估编译器对OpenMP软错误弹性的影响

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00055

Jonas Gava, Vitor V. Bandeira, R. Reis, Luciano Ost

引用次数: 7

Deep Learning for Edge Computing: Current Trends, Cross-Layer Optimizations, and Open Research Challenges 边缘计算的深度学习:当前趋势、跨层优化和开放研究挑战

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00105

Alberto Marchisio, Muhammad Abdullah Hanif, Faiq Khalid, George Plastiras, C. Kyrkou, T. Theocharides, M. Shafique

引用次数: 67

Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach? 在内存处理平台中加速深度神经网络:模拟还是数字方法?

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00044

Shaahin Angizi, Zhezhi He, D. Reis, X. Hu, Wilman Tsai, Shy-Jay Lin, Deliang Fan

{"title":"Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?","authors":"Shaahin Angizi, Zhezhi He, D. Reis, X. Hu, Wilman Tsai, Shy-Jay Lin, Deliang Fan","doi":"10.1109/ISVLSI.2019.00044","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00044","url":null,"abstract":"Nowadays, research topics on AI accelerator designs have attracted great interest, where accelerating Deep Neural Network (DNN) using Processing-in-Memory (PIM) platforms is an actively-explored direction with great potential. PIM platforms, which simultaneously aims to address power- and memory-wall bottlenecks, have shown orders of performance enhancement in comparison to the conventional computing platforms with Von-Neumann architecture. As one direction of accelerating DNN in PIM, resistive memory array (aka. crossbar) has drawn great research interest owing to its analog current-mode weighted summation operation which intrinsically matches the dominant Multiplication-and-Accumulation (MAC) operation in DNN, making it one of the most promising candidates. An alternative direction for PIM-based DNN acceleration is through bulk bit-wise logic operations directly performed on the content in digital memories. Thanks to the high fault-tolerant characteristic of DNN, the latest algorithmic progression successfully quantized DNN parameters to low bit-width representations, while maintaining competitive accuracy levels. Such DNN quantization techniques essentially convert MAC operation to much simpler addition/subtraction or comparison operations, which can be performed by bulk bit-wise logic operations in a highly parallel fashion. In this paper, we build a comprehensive evaluation framework to quantitatively compare and analyze aforementioned PIM based analog and digital approaches for DNN acceleration.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"79 1","pages":"197-202"},"PeriodicalIF":0.0,"publicationDate":"2019-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83770302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Towards Efficient Compact Network Training on Edge-Devices 基于边缘设备的高效紧凑网络训练

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00020

Feng Xiong, Fengbin Tu, S. Yin, Shaojun Wei

{"title":"Towards Efficient Compact Network Training on Edge-Devices","authors":"Feng Xiong, Fengbin Tu, S. Yin, Shaojun Wei","doi":"10.1109/ISVLSI.2019.00020","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00020","url":null,"abstract":"Currently, there is a trend to deploy training on edge devices, which is crucial to future AI applications in various scenarios with transfer and online learning demands. Specifically, there may be a severe degradation of accuracy when directly deploying the trained models on edge devices, because the local environment forms an edge local dataset that is often different from the generic dataset. However, training on edge devices with limited computing and memory capability is a challenge problem. In this paper, we propose a novel quantization training framework for efficient compact network training on edge devices. Firstly, training-aware symmetric quantization is introduced to quantize all of the data types in the training process. Then, channel-wise quantization method is adopted for comapact network quantization, which has significantly high tolerance to quantization errors and can make the training process more stable. For further efficient training, we build a hardware evaluation platform to evaluate different settings of the network, so as to achieve a better trade-off among accuracy, energy and latency. Finally, we evaluate two widely used compact networks on a domain adaptation dataset for image classification, and the results demonstrate that the proposed methods can allow us achieve an improvement of 8.4 × -17.2× in energy reduction and 11.9 × -16.3× in latency reduction compared with 32-bit implementations, while maintaining the classification accuracy.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"306 1","pages":"61-67"},"PeriodicalIF":0.0,"publicationDate":"2019-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77127026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Effect of Loop Positions on Reliability and Attack Resistance of Feed-Forward PUFs 环路位置对前馈puf可靠性和抗攻击能力的影响

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00073

S. V. S. Avvaru, K. Parhi

{"title":"Effect of Loop Positions on Reliability and Attack Resistance of Feed-Forward PUFs","authors":"S. V. S. Avvaru, K. Parhi","doi":"10.1109/ISVLSI.2019.00073","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00073","url":null,"abstract":"In this paper, we study multiplexer (MUX) based feed-forward (FF) physical unclonable functions (FF PUFs) with 64 stages. This paper provides the first systematic empirical analysis of the effect of FF PUF design choices on their performance by evaluating various FF PUF structures in terms of their reliability and attack resistance. To this end, the change in reliability is studied by varying the location of FF loops and varying the number of loops within the circuit. It is observed adding more loops and arbiters makes PUFs more susceptible to noise; FF PUFs with 5 intermediate arbiters can have reliability values that are as low as 81%. It is further demonstrated that a soft-response thresholding strategy can significantly increase the reliability during authentication to more than 96%. We also show that attack resistance can change as a consequence of relative positioning of the FF loops. In case of double-loop FF PUFs (one intermediate arbiter with two utputs), it is shown that appropriately choosing the input and output locations of the FF loops, the number of challenge-response pairs required to attack can be increased by 7 times and can be further increased by 15 times if two intermediate arbiters are used.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"76 1","pages":"366-371"},"PeriodicalIF":0.0,"publicationDate":"2019-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78688023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Neuromorphic Image Sensor Design with Region-Aware Processing 基于区域感知处理的神经形态图像传感器设计

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00089

Md Jubaer Hossain Pantho, Pankaj Bhowmik, C. Bobda

引用次数: 1

Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes 重点是什么需要:面积和功率效率的fpga使用受限开关箱

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00115

Fatemeh Serajeh-hassani, Mohammad Sadrosadati, S. Pointner, R. Wille, H. Sarbazi-Azad

引用次数: 0

Memory Locking: An Automated Approach to Processor Design Obfuscation 内存锁定:处理器设计混淆的一种自动化方法

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00103

Michael Zuzak, Ankur Srivastava

引用次数: 4

Machine Learning Based IoT Edge Node Security Attack and Countermeasures 基于机器学习的物联网边缘节点安全攻击及对策

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00124

Vishalini R. Laguduva, S. A. Islam, Sathyanarayanan N. Aakur, S. Katkoori, Robert Karam

{"title":"Machine Learning Based IoT Edge Node Security Attack and Countermeasures","authors":"Vishalini R. Laguduva, S. A. Islam, Sathyanarayanan N. Aakur, S. Katkoori, Robert Karam","doi":"10.1109/ISVLSI.2019.00124","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00124","url":null,"abstract":"Advances in technology have enabled tremendous progress in the development of a highly connected ecosystem of ubiquitous computing devices collectively called the Internet of Things (IoT). Ensuring the security of IoT devices is a high priority due to the sensitive nature of the collected data. Physically Unclonable Functions (PUFs) have emerged as critical hardware primitive for ensuring the security of IoT nodes. Malicious modeling of PUF architectures has proven to be difficult due to the inherently stochastic nature of PUF architectures. Extant approaches to malicious PUF modeling assume that a priori knowledge and physical access to the PUF architecture is available for malicious attack on the IoT node. However, many IoT networks make the underlying assumption that the PUF architecture is sufficiently tamper-proof, both physically and mathematically. In this work, we show that knowledge of the underlying PUF structure is not necessary to clone a PUF. We present a novel non-invasive, architecture independent, machine learning attack for strong PUF designs with a cloning accuracy of 93.5% and improvements of up to 48.31% over an alternative, two-stage brute force attack model. We also propose a machine-learning based countermeasure, discriminator, which can distinguish cloned PUF devices and authentic PUFs with an average accuracy of 96.01%. The proposed discriminator can be used for rapidly authenticating millions of IoT nodes remotely from the cloud server.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"670-675"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84070138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13