{"title":"环路位置对前馈puf可靠性和抗攻击能力的影响","authors":"S. V. S. Avvaru, K. Parhi","doi":"10.1109/ISVLSI.2019.00073","DOIUrl":null,"url":null,"abstract":"In this paper, we study multiplexer (MUX) based feed-forward (FF) physical unclonable functions (FF PUFs) with 64 stages. This paper provides the first systematic empirical analysis of the effect of FF PUF design choices on their performance by evaluating various FF PUF structures in terms of their reliability and attack resistance. To this end, the change in reliability is studied by varying the location of FF loops and varying the number of loops within the circuit. It is observed adding more loops and arbiters makes PUFs more susceptible to noise; FF PUFs with 5 intermediate arbiters can have reliability values that are as low as 81%. It is further demonstrated that a soft-response thresholding strategy can significantly increase the reliability during authentication to more than 96%. We also show that attack resistance can change as a consequence of relative positioning of the FF loops. In case of double-loop FF PUFs (one intermediate arbiter with two utputs), it is shown that appropriately choosing the input and output locations of the FF loops, the number of challenge-response pairs required to attack can be increased by 7 times and can be further increased by 15 times if two intermediate arbiters are used.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"76 1","pages":"366-371"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Effect of Loop Positions on Reliability and Attack Resistance of Feed-Forward PUFs\",\"authors\":\"S. V. S. Avvaru, K. Parhi\",\"doi\":\"10.1109/ISVLSI.2019.00073\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we study multiplexer (MUX) based feed-forward (FF) physical unclonable functions (FF PUFs) with 64 stages. This paper provides the first systematic empirical analysis of the effect of FF PUF design choices on their performance by evaluating various FF PUF structures in terms of their reliability and attack resistance. To this end, the change in reliability is studied by varying the location of FF loops and varying the number of loops within the circuit. It is observed adding more loops and arbiters makes PUFs more susceptible to noise; FF PUFs with 5 intermediate arbiters can have reliability values that are as low as 81%. It is further demonstrated that a soft-response thresholding strategy can significantly increase the reliability during authentication to more than 96%. We also show that attack resistance can change as a consequence of relative positioning of the FF loops. In case of double-loop FF PUFs (one intermediate arbiter with two utputs), it is shown that appropriately choosing the input and output locations of the FF loops, the number of challenge-response pairs required to attack can be increased by 7 times and can be further increased by 15 times if two intermediate arbiters are used.\",\"PeriodicalId\":6703,\"journal\":{\"name\":\"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)\",\"volume\":\"76 1\",\"pages\":\"366-371\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-07-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2019.00073\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2019.00073","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Effect of Loop Positions on Reliability and Attack Resistance of Feed-Forward PUFs
In this paper, we study multiplexer (MUX) based feed-forward (FF) physical unclonable functions (FF PUFs) with 64 stages. This paper provides the first systematic empirical analysis of the effect of FF PUF design choices on their performance by evaluating various FF PUF structures in terms of their reliability and attack resistance. To this end, the change in reliability is studied by varying the location of FF loops and varying the number of loops within the circuit. It is observed adding more loops and arbiters makes PUFs more susceptible to noise; FF PUFs with 5 intermediate arbiters can have reliability values that are as low as 81%. It is further demonstrated that a soft-response thresholding strategy can significantly increase the reliability during authentication to more than 96%. We also show that attack resistance can change as a consequence of relative positioning of the FF loops. In case of double-loop FF PUFs (one intermediate arbiter with two utputs), it is shown that appropriately choosing the input and output locations of the FF loops, the number of challenge-response pairs required to attack can be increased by 7 times and can be further increased by 15 times if two intermediate arbiters are used.