2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献_第3页

Hot-carrier and BTI damage distinction for high performance digital application in 28nm FDSOI and 28nm LP CMOS nodes 28nm FDSOI和28nm LP CMOS节点中高性能数字应用的热载流子和BTI损伤区分

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604669

A. Bravaix, M. Saliva, F. Cacho, X. Federspiel, C. Ndiaye, S. Mhira, E. Kussener, E. Pauly, V. Huard

引用次数: 3

A high performance scan flip-flop design for serial and mixed mode scan test 用于串行和混合模式扫描测试的高性能扫描触发器设计

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604709

Satyadev Ahlawat, Jaynarayan T. Tudu, A. Matrosova, Virendra Singh

{"title":"A high performance scan flip-flop design for serial and mixed mode scan test","authors":"Satyadev Ahlawat, Jaynarayan T. Tudu, A. Matrosova, Virendra Singh","doi":"10.1109/IOLTS.2016.7604709","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604709","url":null,"abstract":"Over the years, serial scan design has became the defacto Design for Testability (DFT) technique. The ease of testing and high test coverage has made it to gain wide spread industrial acceptance. However, there are associated penalties with serial scan. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of scan design is due to the scan multiplexers added to the inputs of every flip-flop. In today's very high speed designs with minimum possible combinational depth, the performance degradation caused by scan multiplexer has became magnified. Hence to maintain the circuit performance the timing overhead of scan design must be addressed. In this paper we propose a new scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer off the functional path. The proposed design can help in improving the functional frequency of performance critical designs. Furthermore, the proposed design can be used as a common scan flip-flop in mixed mode scan test wherein it can be used as a serial scan cell as well as random access scan RAS) cell.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"34 1","pages":"233-238"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91008221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

On-line write margin estimator to monitor performance degradation in SRAM cores 在线写余量估计器监测SRAM内核的性能退化

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604678

B. Alorda, C. Carmona, G. Torrens, S. Bota

引用次数: 14

ACM: Accurate crosstalk modeling to predict channel delay in Network-on-Chips 准确的串扰建模以预测片上网络中的信道延迟

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604659

Zeinab Mahdavi, Z. Shirmohammadi, S. Miremadi

引用次数: 7

Analysis of BTI aging of level shifters 调位器BTI老化分析

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604662

Jiajing Cai, Basel Halak, Daniele Rossi

引用次数: 5

A fault-tolerant sequential circuit design for SAFs and PDFs soft errors 一种针对saf和pdf软错误的容错顺序电路设计

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604658

A. Matrosova, S. Ostanin, I. Kirienko, E. Nikolaeva

引用次数: 4

A hybrid self-diagnosis mechanism with defective nodes locating and attack detection for parallel computing systems 并行计算系统缺陷节点定位与攻击检测的混合自诊断机制

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604711

Lake Bu, M. Karpovsky

{"title":"A hybrid self-diagnosis mechanism with defective nodes locating and attack detection for parallel computing systems","authors":"Lake Bu, M. Karpovsky","doi":"10.1109/IOLTS.2016.7604711","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604711","url":null,"abstract":"In recent years parallel computing has been widely employed for both science research and commercial applications. For parallel systems such as many-core or computer clusters, it is inevitable to have one or more computing node failures due to random errors or injected attacks. Usually a diagnosis mechanism is able to locate several defective nodes through a number of tests and the analysis of those test signatures (syndromes). Although this covers the cases caused by random errors, sophisticated attacks are still able to manipulate the outputs of each node, so that they will be masked and pass the diagnosis. Therefore in this paper we propose a hybrid self-diagnosis mechanism. We adopt a new type of analysis with the linear syndromes, which are able to locate up to a certain number of defective nodes caused by random errors. In addition to this, we introduce a new type of robust analysis of the non-linear syndromes, which is capable of detecting the attacks undetectable by the linear syndromes at a probability close to one. Moreover, since this hybrid self-diagnosis mechanism is on the data level which makes little distinction among different operating systems and programming languages, it can be migrated onto any other platforms conveniently.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"28 1","pages":"245-250"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88158578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Hardware enlightening: No where to hide your Hardware Trojans! 硬件启蒙:没有地方隐藏你的硬件木马!

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604712

Mohammad Saleh Samimi, Ehsan Aerabi, Z. Kazemi, M. Fazeli, A. Patooghy

引用次数: 20

Feasibility of software-based repair for program memories 基于软件的程序存储器修复的可行性

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604699

Patryk Skoncej, F. Mühlbauer, Felix Kubicek, Lukas Schröder, Mario Schölzel

引用次数: 2

Power-side-channel analysis of carbon nanotube FET based design 基于功率侧通道分析的碳纳米管场效应管设计

2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2016-07-04 DOI: 10.1109/IOLTS.2016.7604705

Chandra K. H. Suresh, Bodhisatwa Mazumdar, Subidh Ali, O. Sinanoglu

{"title":"Power-side-channel analysis of carbon nanotube FET based design","authors":"Chandra K. H. Suresh, Bodhisatwa Mazumdar, Subidh Ali, O. Sinanoglu","doi":"10.1109/IOLTS.2016.7604705","DOIUrl":"https://doi.org/10.1109/IOLTS.2016.7604705","url":null,"abstract":"Continuous scaling of CMOS technology beyond sub-nanometer region has aggravated short-channel effects, resulting in increased leakage current and high power densities. Furthermore, elevated leakage current and power density render CMOS based security-critical applications vulnerable to power-side-channel attacks. Carbon Nanotubes (CNT) is a promising alternative to CMOS technology. It offers superior transport properties, excellent thermal conductivities, high current capacities, and low power densities. Besides area, power and performance, adherence to hardware security aspects have become an important criteria today. In this work, we present the first study on power-side-channel analysis of ciphers implemented using CNTFETs. Our simulation results show that for 130 power traces, the simple power analysis (SPA) attack success rate is less than 0.35 for CNTFET based ciphers, whereas it is greater than 0.95 for CMOS based ciphers. For correlation power analysis, the difference of correlation coefficient of the correct key and closest wrong key guess is 1.3 for CMOS based design, and less than 0.56 for CNTFET based ciphers for 20,000 power traces, which implies lesser distinguishability of correct key in case of CNTFETs. These results indicate that CNT offers a higher resilience to power-side-channel attacks than CMOS.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"47 1","pages":"215-218"},"PeriodicalIF":0.0,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77579229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2