A. Matrosova, S. Ostanin, I. Kirienko, E. Nikolaeva
{"title":"一种针对saf和pdf软错误的容错顺序电路设计","authors":"A. Matrosova, S. Ostanin, I. Kirienko, E. Nikolaeva","doi":"10.1109/IOLTS.2016.7604658","DOIUrl":null,"url":null,"abstract":"This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has a self-checking sequential circuit, a not self-testing checker and a normal (unprotected) sequential circuit. It is proved the reliability properties of the suggested scheme both for single stuck-at faults at gate poles and path delay faults transient and intermittent.","PeriodicalId":6580,"journal":{"name":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"35 1","pages":"5-6"},"PeriodicalIF":0.0000,"publicationDate":"2016-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A fault-tolerant sequential circuit design for SAFs and PDFs soft errors\",\"authors\":\"A. Matrosova, S. Ostanin, I. Kirienko, E. Nikolaeva\",\"doi\":\"10.1109/IOLTS.2016.7604658\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has a self-checking sequential circuit, a not self-testing checker and a normal (unprotected) sequential circuit. It is proved the reliability properties of the suggested scheme both for single stuck-at faults at gate poles and path delay faults transient and intermittent.\",\"PeriodicalId\":6580,\"journal\":{\"name\":\"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)\",\"volume\":\"35 1\",\"pages\":\"5-6\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-07-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IOLTS.2016.7604658\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IOLTS.2016.7604658","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fault-tolerant sequential circuit design for SAFs and PDFs soft errors
This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has a self-checking sequential circuit, a not self-testing checker and a normal (unprotected) sequential circuit. It is proved the reliability properties of the suggested scheme both for single stuck-at faults at gate poles and path delay faults transient and intermittent.