On-line write margin estimator to monitor performance degradation in SRAM cores

Abstract

SRAM cell sensitivity to process variation increases aggressively with technology scaling trends. Long-term aging parameter variability degrades 6T-SRAM cells performance in the nanometre era. More accurate and non-invasive methodologies must be provided to extend the free-failure period for high reliability systems. This paper proposes a Word-Line Voltage Margin estimator to observe SRAM performance degradation. The proposed on-line estimator approach does not require memory array modification and it can be shared with all embedded memories in a SoC reducing its area overhead.