A fault-tolerant sequential circuit design for SAFs and PDFs soft errors

Abstract

This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has a self-checking sequential circuit, a not self-testing checker and a normal (unprotected) sequential circuit. It is proved the reliability properties of the suggested scheme both for single stuck-at faults at gate poles and path delay faults transient and intermittent.