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CNN-Based Bi-Directional Motion Compensation for High Efficiency Video Coding 基于cnn的双向运动补偿高效视频编码
2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351189
Zhenghui Zhao, Shiqi Wang, Shanshe Wang, Xinfeng Zhang, Siwei Ma, Jiansheng Yang
{"title":"CNN-Based Bi-Directional Motion Compensation for High Efficiency Video Coding","authors":"Zhenghui Zhao, Shiqi Wang, Shanshe Wang, Xinfeng Zhang, Siwei Ma, Jiansheng Yang","doi":"10.1109/ISCAS.2018.8351189","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351189","url":null,"abstract":"The state-of-the-art High Efficiency Video Coding (HEVC) standard adopts the bi-prediction to improve the coding efficiency for B frame. However, the underlying assumption of this technique is that the motion field is characterized by the block-wise translational motion model, which may not be efficient in the challenging scenarios such as rotation and deformation. Inspired by the excellent signal level prediction capability of deep learning, we propose a bi-directional motion compensation algorithm with convolutional neural network, which is further incorporated into the video coding pipeline to improve the performance of video compression. Our network consists of six convolutional layers and a skip connection, which integrates the prediction error detection and non-linear signal prediction into an end-to-end framework. Experimental results show that by incorporating the proposed scheme into HEVC, up to 10.5% BD-rate savings and 3.1% BD-rate savings on average for random access (RA) configuration have been observed.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"7 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89661427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Coming Up N3XT, After 2D Scaling of Si CMOS 即将到来的N3XT，在Si CMOS的二维缩放之后
2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351756
William Hwang, W. Wan, S. Mitra, H. Wong
{"title":"Coming Up N3XT, After 2D Scaling of Si CMOS","authors":"William Hwang, W. Wan, S. Mitra, H. Wong","doi":"10.1109/ISCAS.2018.8351756","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351756","url":null,"abstract":"As two-dimensional scaling of Si CMOS crosses the nanometer threshold, from 7 nm, 5 nm, 3 nm, toward 1 nm technology nodes, will it continue to provide the energy efficiency required of future computing systems? A scalable, fast, and energy-efficient computation platform that may provide another 1,000× in computing energy efficiency (energy-execution time product) will have massive on-chip memory co-located with highly energy-efficient computing logic, enabled by 3D integration (e.g., monolithic) with ultra-dense and fine-grained connectivity. There will be multiple layers of memories interleaved with computing logic, sensors, and application-specific devices. We call this technology platform N3XT, Nano-engineered Computing Systems Technology. In this paper, we give an overview of the nanoscale memory and logic technologies that enable N3XT.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"81 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83983281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Live Demonstration: Front and Back Illuminated Dynamic and Active Pixel Vision Sensors Comparison 现场演示:前后照明动态和主动像素视觉传感器的比较
2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351314
Gemma Taverni, Diederik Paul Moeys, Chenghan Li, T. Delbrück, C. Cavaco, V. Motsnyi, D. S. S. Bello
{"title":"Live Demonstration: Front and Back Illuminated Dynamic and Active Pixel Vision Sensors Comparison","authors":"Gemma Taverni, Diederik Paul Moeys, Chenghan Li, T. Delbrück, C. Cavaco, V. Motsnyi, D. S. S. Bello","doi":"10.1109/ISCAS.2018.8351314","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351314","url":null,"abstract":"The demonstration shows the differences between two novel Dynamic and Active Pixel Vision Sensors (DAVIS). While both sensors are based on the same circuits and have the same resolution (346×260), they differ in their manufacturing. The first sensor is a DAVIS with standard Front Side Illuminated (FSI) technology and the second sensor is the first Back Side Illuminated (BSI) DAVIS sensor.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"71 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84015848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of a radiation-tolerant high-speed driver for Mach Zender Modulators in High Energy Physics 高能物理中马赫增德调制器耐辐射高速驱动器的设计
2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351491
G. Magazzú, G. Ciarpi, S. Saponara
{"title":"Design of a radiation-tolerant high-speed driver for Mach Zender Modulators in High Energy Physics","authors":"G. Magazzú, G. Ciarpi, S. Saponara","doi":"10.1109/ISCAS.2018.8351491","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351491","url":null,"abstract":"This paper presents the integrated circuit design, targeting a CMOS 65 nm 1.2 V technology, of a high-speed driver that provides the differential input signals to a Mach Zender Modulator (MZM), and allows tuning of the MZM operating point through adjustment of the bias voltage. A multi-voltage domain circuit is proposed, where each domain is isolated through deep n-well trenches, to face the high voltage swing and the bias regulation requirements of the MZM. The MZM device, whose prototype has been implemented in silicon photonics iSiPP50G technology, is emerging as a promising solution for radiation tolerant, several hundreds of Mrad, and high-speed, in the range of 10 Gbps, optical links. These stringent requirements are needed in high energy physics experiments in the upgrade of the Large Hadron Collider or in future Linear Colliders.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86667077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Optimizing an Analog Neuron Circuit Design for Nonlinear Function Approximation 非线性函数逼近模拟神经元电路的优化设计
2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351459
Alexander Neckar, T. Stewart, B. Benjamin, K. Boahen
{"title":"Optimizing an Analog Neuron Circuit Design for Nonlinear Function Approximation","authors":"Alexander Neckar, T. Stewart, B. Benjamin, K. Boahen","doi":"10.1109/ISCAS.2018.8351459","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351459","url":null,"abstract":"Silicon neurons designed using subthreshold analog-circuit techniques offer low power and compact area but are exponentially sensitive to threshold-voltage mismatch in transistors. The resulting heterogeneity in the neurons' responses, however, provides a diverse set of basis functions for smooth nonlinear function approximation. For low-order polynomials, neuron spiking thresholds ought to be distributed uniformly across the function's domain. This uniform distribution is difficult to achieve solely by sizing transistors to titrate mismatch. With too much mismatch, many neuron's thresholds fall outside the domain (i.e. they either always spike or remain silent). With too little mismatch, all their thresholds bunch up in the middle of the domain. Here, we present a silicon-neuron design methodology that minimizes overall area by optimizing transistor sizes in concert with a few locally-stored programmable bits to adjust each neuron's offset (and gain). We validated this methodology in a 28-nm mixed analog-digital CMOS process. Compared to relying on mismatch alone, augmentation with digital correction effectively reduced silicon area by 38%.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"47 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86923620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Power Reduction in Incremental ΔΣ ADCs Using a Capacitor Scaling Technique 利用电容缩放技术降低增量式ΔΣ adc的功耗
2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351289
Saqib Mohamad, Moaaz Ahmed, Jie Yuan, A. Bermak
{"title":"Power Reduction in Incremental ΔΣ ADCs Using a Capacitor Scaling Technique","authors":"Saqib Mohamad, Moaaz Ahmed, Jie Yuan, A. Bermak","doi":"10.1109/ISCAS.2018.8351289","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351289","url":null,"abstract":"Incremental analog to digital converters (IADCs) are aimed at converting low frequency signals with high accuracy. The operational transconductance amplifiers (OTAs) used to implement the integrators are the dominant source of power consumption, since they must settle to a desired accuracy within a given clock period, by driving a capacitive load. Reducing the capacitor size correspondingly increases the thermal noise power which reduces the signal-to-noise ratio (SNR) of the ADC. In this paper, we introduce a capacitor scaling technique which exploits the uneven weightage of the IADC decimation filter on the output bit-stream of the IADC. The power consumption can be scaled down correspondingly but the noise power does not increase by the same extent, leading to greater energy efficiency. A second order feedforward IADC is simulated to demonstrate the idea, which achieves up to a 25% improvement in energy efficiency using the proposed scheme.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"11 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86930761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design Considerations for Integrated, High-Voltage DC-DC Converters 集成高压DC-DC转换器的设计注意事项
2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351566
A. Salimath, Giovanni Gonano, E. Bonizzoni, D. Brambilla, E. Botti, F. Maloberti
{"title":"Design Considerations for Integrated, High-Voltage DC-DC Converters","authors":"A. Salimath, Giovanni Gonano, E. Bonizzoni, D. Brambilla, E. Botti, F. Maloberti","doi":"10.1109/ISCAS.2018.8351566","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351566","url":null,"abstract":"This paper presents two design considerations for integrated high-voltage DC-DC converters in automobile and industrial applications. The proposed solutions include (i) a quasi soft-start technique using over-current protection (OCP) circuits and limited duty cycle control and (ii) a technique to drive a floating load-side switch that suppresses the effect of bond-wire bouncing on its gate-source voltage. The first technique avoids the conventional, overhead start-up circuits and significantly reduces the converter startup time. The second technique gains importance primarily from device reliability viewpoint in high-voltage (HV) conditions. The effectiveness of the proposed techniques has been verified with simulations at the transistor level using a 110-nm BCD technology.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"16 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87030151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Epidemic spreading in multiplex networks with Markov and memory based inter-layer dynamics 基于马尔可夫和记忆的层间动力学的多路网络中的流行病传播
2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351135
Miroslav Mirchev, I. Mishkovski, L. Kocarev
{"title":"Epidemic spreading in multiplex networks with Markov and memory based inter-layer dynamics","authors":"Miroslav Mirchev, I. Mishkovski, L. Kocarev","doi":"10.1109/ISCAS.2018.8351135","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351135","url":null,"abstract":"Many spreading processes of information and diseases take place over complex networks that are composed of multiple interconnection layers. The relationship between network structure, nodes' activity and spreading dynamics impose a threshold above which an epidemic endures. The network structure of individual layers can take different forms, such as scale-free or random, which significantly impacts the epidemic threshold. Similarly, the nodes' inter-layer transition dynamics largely influences the threshold as well. In this study we consider an inter-layer dynamics following: a Markov process, and a memory based activity creating inter-event times with a heavy-tail distribution, which are typically observed in human behavior. It is shown that by introducing a layer of inactivity the epidemic threshold can be closely predicted with our previously derived expression for multiplex networks.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"40 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85449069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Producing Complex Networks Using Coupled Oscillatory Circuits with Evolutionary Connections 利用具有进化连接的耦合振荡电路产生复杂网络
2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351665
Y. Uwate, T. Ott, Y. Nishio
{"title":"Producing Complex Networks Using Coupled Oscillatory Circuits with Evolutionary Connections","authors":"Y. Uwate, T. Ott, Y. Nishio","doi":"10.1109/ISCAS.2018.8351665","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351665","url":null,"abstract":"In this study, we propose a method of generating complex networks by exploiting synchronization between coupled oscillatory circuits. To each node of a 2D fully connected network a van der Pol oscillator is assigned. We then study the topological evolution of the network in dependence on environmental conditions. These conditions are modeled by considering the distance between the oscillators and some small frequency errors that are added. By carrying out computer simulations, we confirm that different types of complex networks are obtained depending on different environmental conditions.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"287 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86415974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Exploiting the non-linear current-voltage characteristics for resistive memory readout 利用电阻式存储器读出的非线性电流-电压特性
2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351490
N. Papandreou, A. Sebastian, H. Pozidis
{"title":"Exploiting the non-linear current-voltage characteristics for resistive memory readout","authors":"N. Papandreou, A. Sebastian, H. Pozidis","doi":"10.1109/ISCAS.2018.8351490","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351490","url":null,"abstract":"Various resistive memory technologies are finding application in the space of storage-class memory and emerging non-von Neumann computing systems. For both applications, a key enabling technology is the ability to store multiple resistance levels in a single memory cell. The resistance states of these devices are typically measured in the low-field regime, where the electrical transport can be assumed to be Ohmic. However, when biased at slightly higher voltages, they exhibit significantly nonlinear I-V characteristics. In this paper, we demonstrate how this field dependence of the resistance values can be exploited in various applications. We present simulation and experimental results where readout schemes based on the non-linear I-V behavior are used to enhance the readout margin and also to compensate for resistance drift.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"2 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87339908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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