2018 IEEE International Symposium on Circuits and Systems (ISCAS)最新文献_第9页

Fully-Differential Universal Frequency Filter with Dual-Parameter Control of the Pole Frequency and Quality Factor 极点频率和品质因子双参数控制的全差分通用频率滤波器

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351005

L. Langhammer, R. Sotner, Jan Dvorak, J. Jerabek, Miroslav Zapletal

引用次数: 2

A Novel Sensing Circuit with Large Sensing Margin for Embedded Spin-Transfer Torque MRAMs 嵌入式自旋传递转矩mram的大裕度传感电路

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351577

Leila Bagheriye, S. Toofan, R. Saeidi, F. Moradi

引用次数: 7

Enhancing Fundamental Energy Limits of Field-Coupled Nanocomputing Circuits 增强场耦合纳米计算电路的基本能量限制

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351150

Jeferson F. Chaves, M. A. Ribeiro, F. Sill, O. V. Neto

引用次数: 6

A 35μW 64 × 64 Pixels Vision Sensor Embedding Local Binary Pattern Code Computation 35μW 64 × 64像素视觉传感器嵌入局部二进制模式代码的计算

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351037

M. Gottardi, M. Lecca

引用次数: 1

A Sub-pico Joules Per Bit Robust Physical Unclonable Function Based on Subthreshold Voltage References 基于亚阈值电压参考的亚微焦耳/比特鲁棒物理不可克隆函数

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351253

Yuan Cao, Chip-Hong Chang, Wenhan Zheng, Xiaojin Zhao

{"title":"A Sub-pico Joules Per Bit Robust Physical Unclonable Function Based on Subthreshold Voltage References","authors":"Yuan Cao, Chip-Hong Chang, Wenhan Zheng, Xiaojin Zhao","doi":"10.1109/ISCAS.2018.8351253","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351253","url":null,"abstract":"Low power, lightweight and robust physical unclonable function (PUF) is a sought-after for IoT device identification/authentication. This paper presents a low power PUF design with high reliability against temperature and supply voltage variations. A response bit is extracted by comparing a pair of identically designed subthreshold voltage references. The voltage difference due to device mismatch is digitized and registered in a bidirectional counter, which can be used to identify and filter out the unstable response bits. The readout circuit works in tandem with the proposed double sampling technique to reduce the bias of components that are not the main entropy source of response bits. The proposed design is evaluated by extensive simulation using standard 65 nm CMOS process. It consumes merely 0.16 pJ/bit. The simulated uniqueness is an almost ideal 50.03%. Due to the intrinsic stability of voltage references, the reliability of its native response is 98.17% for the supply voltage variation from 1 V to 1.4 V and 97.60% for the temperature variation from 0 ° C to 80 °C. The generated response bitstream has passed both the autocorrelation test and NIST randomness test.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90576173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems 用于神经形态系统中低延迟芯片间通信的双向地址-事件收发器块

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351623

Ning Qiao, G. Indiveri

{"title":"A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems","authors":"Ning Qiao, G. Indiveri","doi":"10.1109/ISCAS.2018.8351623","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351623","url":null,"abstract":"Neuromorphic systems typically use the Address-Event Representation (AER) to transmit signals among nodes, cores, and chips. Communication of Address-Events (AEs) between neuromorphic cores/chips typically requires two parallel digital signal buses for Input/Output (I/O) operations. This requirement can become very expensive for large-scale systems in terms of both dedicated I/O pins and power consumption. In this paper we present a compact fully asynchronous event-driven transmitter/receiver block that is both power efficient and I/O efficient. This block implements high-throughput low-latency bi-directional communication through a parallel AER bus. We show that by placing the proposed AE transceiver block in two separate chips and linking them by a single AER bus, we can drive the communication and switch the transmission direction of the shared bus on a single event basis, from either side with low-latency. We present experimental results that validate the circuits proposed and demonstrate reliable bi-directional event transmission with high-throughput. The proposed AE block, integrated in a neuromorphic chip fabricated using a 28 nm FDSOI process, occupies a silicon die area of 140 μm × 70 μm. The experimental measurements show that the event-driven AE block combined with standard digital I/Os has a direction switch latency of 5 ns and can achieve a worst-case bi-directional event transmission throughput of 28.6M Events/second while consuming 11 pJ per event (26-bit) delivery.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"73 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83933784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

The Role of Memories in Transprecision Computing 记忆在精确计算中的作用

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351768

C. Weis, Matthias Jung, Éder F. Zulian, C. Sudarshan, Deepak M. Mathew, N. Wehn

引用次数: 3

Active IC Metering of Digital Signal Processing Subsystem with Two-Tier Activation for Secure Split Test 数字信号处理分系统安全分离测试两层激活有源IC计量

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351390

S. Dhabu, Yue Zheng, Wenye Liu, Chip-Hong Chang

引用次数: 0

A Speed Planner Approach Based On Bézier Curves Using Vehicle Dynamic Constrains and Passengers Comfort 一种考虑车辆动力学约束和乘客舒适度的bassazier曲线速度规划方法

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351307

Ray Lattarulo, E. Martí, M. Marcano, Jose A. Matute, Joshué Pérez

引用次数: 13

Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing 前缀序列:用模拟退火优化并行前缀加法器

2018 IEEE International Symposium on Circuits and Systems (ISCAS) Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351414

Takayuki Moto, M. Kaneko

引用次数: 4