130nm SiGe BiCMOS中60ghz全差分倍频器的分析与设计

V. Riess, P. V. Testa, C. Carta, F. Ellinger
{"title":"130nm SiGe BiCMOS中60ghz全差分倍频器的分析与设计","authors":"V. Riess, P. V. Testa, C. Carta, F. Ellinger","doi":"10.1109/ISCAS.2018.8351193","DOIUrl":null,"url":null,"abstract":"This paper presents a fully-differential frequency doubler integrated in 130 nm SiGe BiCMOS technology. To obtain a differential output signal, the conventional push-push topology is extended. The benefits of this approach are investigated with non-linear circuit analysis and discussed. While both the conventional push-push doubler and the Gilbert-cell doubler only suppress the odd harmonics, the extended topology enables the further suppression of the fourth harmonic. The circuit requires a set of phase-shifted versions of the input signal, which are generated on-chip with a polyphase filter. The proposed approach is validated with measurements of the fabricated circuit: an output power of −4 dBm at the 1 dB compression point with a −3 dB output bandwidth of 10 GHz from 55.6 GHz to 65.6 GHz is reported. With a low power consumption of 23.5 mW, a conversion gain of −15 dB and a fundamental suppression of 42 dB are achieved around the center frequency. A method to improve the conversion gain is discussed in the conclusion.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"13 1","pages":"1-5"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Analysis and Design of a 60 GHz Fully-Differential Frequency Doubler in 130 nm SiGe BiCMOS\",\"authors\":\"V. Riess, P. V. Testa, C. Carta, F. Ellinger\",\"doi\":\"10.1109/ISCAS.2018.8351193\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a fully-differential frequency doubler integrated in 130 nm SiGe BiCMOS technology. To obtain a differential output signal, the conventional push-push topology is extended. The benefits of this approach are investigated with non-linear circuit analysis and discussed. While both the conventional push-push doubler and the Gilbert-cell doubler only suppress the odd harmonics, the extended topology enables the further suppression of the fourth harmonic. The circuit requires a set of phase-shifted versions of the input signal, which are generated on-chip with a polyphase filter. The proposed approach is validated with measurements of the fabricated circuit: an output power of −4 dBm at the 1 dB compression point with a −3 dB output bandwidth of 10 GHz from 55.6 GHz to 65.6 GHz is reported. With a low power consumption of 23.5 mW, a conversion gain of −15 dB and a fundamental suppression of 42 dB are achieved around the center frequency. A method to improve the conversion gain is discussed in the conclusion.\",\"PeriodicalId\":6569,\"journal\":{\"name\":\"2018 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"volume\":\"13 1\",\"pages\":\"1-5\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-05-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2018.8351193\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2018.8351193","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

摘要

提出了一种采用130 nm SiGe BiCMOS技术集成的全差分倍频器。为了获得差分输出信号,对传统的推-推拓扑进行了扩展。通过非线性电路分析对这种方法的优点进行了研究和讨论。传统的推推式倍频器和吉尔伯特单元倍频器都只能抑制奇次谐波,而扩展的拓扑结构可以进一步抑制四次谐波。该电路需要输入信号的一组相移版本,这些版本是用多相滤波器在片上生成的。所提出的方法通过制造电路的测量进行了验证:在1db压缩点输出功率为- 4dbm,输出带宽为- 3db,从55.6 GHz到65.6 GHz为10 GHz。在23.5 mW的低功耗下,在中心频率附近实现了- 15 dB的转换增益和42 dB的基波抑制。最后讨论了提高转换增益的方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Analysis and Design of a 60 GHz Fully-Differential Frequency Doubler in 130 nm SiGe BiCMOS
This paper presents a fully-differential frequency doubler integrated in 130 nm SiGe BiCMOS technology. To obtain a differential output signal, the conventional push-push topology is extended. The benefits of this approach are investigated with non-linear circuit analysis and discussed. While both the conventional push-push doubler and the Gilbert-cell doubler only suppress the odd harmonics, the extended topology enables the further suppression of the fourth harmonic. The circuit requires a set of phase-shifted versions of the input signal, which are generated on-chip with a polyphase filter. The proposed approach is validated with measurements of the fabricated circuit: an output power of −4 dBm at the 1 dB compression point with a −3 dB output bandwidth of 10 GHz from 55.6 GHz to 65.6 GHz is reported. With a low power consumption of 23.5 mW, a conversion gain of −15 dB and a fundamental suppression of 42 dB are achieved around the center frequency. A method to improve the conversion gain is discussed in the conclusion.
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