R. Figueras, J. M. Margarit, G. Vergara, V. Villamayor, R. Gutiérrez-Álvarez, C. Fernández-Montojo, L. Terés, F. Serra-Graells
{"title":"A 128× 128-pix 4-kfps 14-bit Digital-Pixel PbSe-CMOS Uncooled MWIR Imager","authors":"R. Figueras, J. M. Margarit, G. Vergara, V. Villamayor, R. Gutiérrez-Álvarez, C. Fernández-Montojo, L. Terés, F. Serra-Graells","doi":"10.1109/ISCAS.2018.8351264","DOIUrl":null,"url":null,"abstract":"This paper presents a 128 × 128-pix high-speed PbSe-CMOS uncooled MWIR imager with pixel digital output. The proposed in-pixel A/D converter based on integrate-and-fire modulation achieves good linearity even at 20 Meps thanks to its soft-reset mechanism. Class-AB CMOS circuits are proposed to keep static power consumption below 10 μW/pix. Each DPS cell also includes its own analog reference and bias generator. The resulting pixel digital-only I/O interface ensures low crosstalk at the FPA level. From post-layout simulation results, the imager is capable of delivering 14 bit up to 1 kfps or alternatively 4 kfps up to 10 bit. The presented MWIR imager is currently being integrated in the 0.18-μm 1P6M CMOS technology from X-FAB.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"3 1","pages":"1-5"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2018.8351264","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a 128 × 128-pix high-speed PbSe-CMOS uncooled MWIR imager with pixel digital output. The proposed in-pixel A/D converter based on integrate-and-fire modulation achieves good linearity even at 20 Meps thanks to its soft-reset mechanism. Class-AB CMOS circuits are proposed to keep static power consumption below 10 μW/pix. Each DPS cell also includes its own analog reference and bias generator. The resulting pixel digital-only I/O interface ensures low crosstalk at the FPA level. From post-layout simulation results, the imager is capable of delivering 14 bit up to 1 kfps or alternatively 4 kfps up to 10 bit. The presented MWIR imager is currently being integrated in the 0.18-μm 1P6M CMOS technology from X-FAB.