2018 IEEE Symposium on VLSI Technology最新文献_第3页

An Energy Efficient FinFET-based Field Programmable Synapse Array (FPSA) Feasible for One-shot Learning on EDGE AI 一种基于finfet的现场可编程突触阵列(FPSA)，可用于EDGE AI的一次学习

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510706

J. L. Kuo, H. W. Chen, E. Hsieh, S. Chung, T. P. Chen, S. A. Huang, J. Chen, O. Cheng

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引用次数: 1

A low-power and high-speed True Random Number Generator using generated RTN 一种低功耗、高速的真随机数发生器

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510671

James Brown, R. Gao, Z. Ji, Jiezhi Chen, Jixuan Wu, Jianfu Zhang, Bo Zhou, Q. Shi, Jacob Crowford, Weidong Zhang

引用次数: 24

22-nm FD-SOI Embedded MRAM with Full Solder Reflow Compatibility and Enhanced Magnetic Immunity 22纳米FD-SOI嵌入式MRAM具有完全焊料回流兼容性和增强的磁抗扰度

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510655

K. Lee, K. Yamane, S. Noh, V. B. Naik, H. Yang, S. Jang, J. Kwon, B. Behin-Aein, R. Chao, J. H. Lim, K. S., K. W. Gan, D. Zeng, N. Thiyagarajah, L. C. Goh, B. Liu, E. Toh, B. Jung, T. L. Wee, T. Ling, T. Chan, N. Chung, J. W. Ting, S. Lakshmipathi, J. Son, J. Hwang, L. Zhang, R. Low, R. Krishnan, T. Kitamura, Y. You, C. Seet, H. Cong, D. Shum, J. Wong, S. Woo, J. Lam, E. Quek, A. See, S. Siah

引用次数: 22

Response Speed of Negative Capacitance FinFETs 负电容finfet的响应速度

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510626

D. Kwon, Y. Liao, Yen-Kai Lin, J. Duarte, K. Chatterjee, A. Tan, A. Yadav, C. Hu, Z. Krivokapic, S. Salahuddin

引用次数: 28

A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node 亚5nm节点负电容场效应管多晶相分布及界面层效应的综合研究

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510696

Y. Tang, C. Su, Y.-S. Wang, K. Kao, T.-L. Wu, P. Sung, F. Hou, C. Wang, M. Yeh, Y. Lee, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang

引用次数: 8

Shaping circuit environment to face the thermal challenge Innovative technologies from low to high power electronics 从低功率到高功率电子产品的创新技术

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510677

P. Coudrain, J. Colonna, L. Collin, R. Prieto, L. Fréchette, J. Barrau, G. Savelli, P. Vivet, Q. Struss, J. Widiez, K. Vladimirova, K. Triantopoulos, H. Beckrich-Ros, M. Vilarrubí, G. Laguna, H. Azarkish, M. Shirazi, J. Michailos

引用次数: 1

Enabling CMOS Scaling Towards 3nm and Beyond 使CMOS向3nm及以上扩展

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510683

A. Mocuta, P. Weckx, S. Demuynck, D. Radisic, Y. Oniki, J. Ryckaert

引用次数: 17

A Novel 3D AND-type NVM Architecture Capable of High-density, Low-power In-Memory Sum-of-Product Computation for Artificial Intelligence Application 面向人工智能应用的高密度、低功耗内存积和计算的新型3D and型NVM架构

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510688

H. Lue, Wei-Chen Chen, Hung-Sheng Chang, Keh-Chung Wang, Chih-Yuan Lu

引用次数: 19

Te-based binary OTS selectors with excellent selectivity (>105), endurance (>108) and thermal stability (>450°C) 具有优异的选择性(>105)、耐久性(>108)和热稳定性(>450°C)的碲基二元OTS选择器

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510681

Jongmyung Yoo, Y. Koo, Solomon Amsalu Chekol, Jaehyuk Park, Jeonghwan Song, H. Hwang

引用次数: 11

Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect 负电容，n沟道，Si finfet:双向低于60 mV/dec，负DIBL，负差分电阻和改进的短沟道效应

2018 IEEE Symposium on VLSI Technology Pub Date : 2018-06-01 DOI: 10.1109/VLSIT.2018.8510691

Hong Zhou, D. Kwon, A. Sachid, Y. Liao, K. Chatterjee, A. Tan, A. Yadav, C. Hu, S. Salahuddin

引用次数: 34