2017 IEEE 67th Electronic Components and Technology Conference (ECTC)最新文献

{"title":"SACQ Solder Board Level Reliability Evaluation and Life Prediction Model for Wafer Level Packages","authors":"Wei Lin, Q. Pham, Bora Baloğlu, Michael Johnson","doi":"10.1109/ECTC.2017.257","DOIUrl":"https://doi.org/10.1109/ECTC.2017.257","url":null,"abstract":"Wafer Level Chip Scale Packaging (WLCSP) designs, including Wafer Level Fan-Out (WLFO) technologies, are gaining more and more applications for next generation small and thin devices. Since the WLCSP and WLFO packages are mounted directly on the motherboard without a substrate as a buffer, the large coefficient of thermal expansion (CTE) mismatch between the silicon die and the motherboard makes the temperature cycle board level reliability (BLR) of WLCSP and WLFO a tremendous challenge, especially for large body sizes. Currently, a tin (Sn)-silver (Ag)-copper (Cu) solder alloy such as SAC405 is commonly used in WLCSP and WLFO designs, but it has difficulty meeting the board level reliability when the footprint exceeds a certain size. As a result, a new type of solder alloy, SACQ, has been developed in recent years to enhance BLR performance. However, there is little published reliability data of how this new SACQ solder performed in actual package applications. There is also lack of a BLR life prediction model for SACQ solder, unlike the other typical eutectic or leadfree solders. In this paper, the board level temperature cycle reliability of SACQ solder is tested with various WLCSP and WLFO packages configurations. The failure modes associated with SACQ solder are evaluated in detail as well. The temperature cycle performance of SACQ solder is also compared to SAC405 solder, and shows significant improvement consistently over all the packages tested. In addition to the empirical study, a BLR life prediction model for SACQ is also developed based on finite element model (FEM). The required SACQ creep material properties, finite element model setup, damage indicator selection, and life prediction model correlation are all described with details in the paper.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"15 1","pages":"1058-1064"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81984745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Local Stress Analysis by XRD Single Crystal Method and Kossel Diffraction Applied to a Flip Chip Structure","authors":"A.-L. Lebaudya, R. Pescia, W. Kpobieb, M. Fendler","doi":"10.1109/ECTC.2017.48","DOIUrl":"https://doi.org/10.1109/ECTC.2017.48","url":null,"abstract":"X-Ray Diffraction (XRD) is a very efficient experimental tool for strain/stress analysis at different scales, which makes possible to carry out some mappings in complex 3D flip chip assemblies. First, with single crystal method, both the chip and the substrate have been analyzed at the same positions, considering a 1mm2 step, in order to quantify the level of stress inside. Then Kossel microdiffraction has been tested for local stress analysis with a spatial resolution of a few micrometers. This method is set up in a Scanning Electron Microscope (SEM) which allows to select precisely the analyzed area, the probe volume is about 1ìm3 and the strain resolution is about 10-4. The work here proposed describes the means employed to perform the different XRD analyses on single crystals used in 3D integration structures, the experimental results are then compared to numerical Finite Elements simulations and are discussed.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"2060-2065"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82491544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal and Electrical Performance of Direct Bond Interconnect Technology for 2.5D and 3D Integrated Circuits","authors":"Akash Agrawal, Shaowu Huang, Guilian Gao, Liang Wang, Javier A. DeLaCruz, L. Mirkarimi","doi":"10.1109/ECTC.2017.341","DOIUrl":"https://doi.org/10.1109/ECTC.2017.341","url":null,"abstract":"Currently thermo-compression bonding (TCB) of solder capped micro bumps is the industry standard for high bandwidth memory (HBM) packaging. However, the assembly complexity and high cost has limited its high volume adoption. In addition to assembly challenges, formation of a brittle intermetallic layer reduces electro migration resistance. Furthermore, the underfill between die nearly doubles the stack height and greatly increases thermal resistance of the stacked dies. Currently the layer count stands at four die stacked on a base die. Adding additional layers to the stack poses additional challenges on assembly and ultimately heat dissipation. Direct Bond Interconnect technology is an attractive alternate solution due to the instantaneous bond at room temperature. Two dielectric surfaces are bonded at room temperature, while the metal interconnection (Cu to Cu in most applications) is completed during a subsequent low temperature anneal (1500C – 3000C). The initial dielectric bonding process is performed at ambient temperature and pressure with no adhesive or other filler materials. Bonding takes place instantaneously once the two surfaces are brought into contact. Batch anneal is carried out in a conventional oven. Compared to thermal compression bonding, it has advantages higher throughput and yield which drive the overall bonding costs down. It leverages foundry-standard copper dual-damascene process to achieve scalable, very low cost-of-ownership 3D-interconnect on die. The technology allows Cu-Cu bonding with no additional thickness to the stack. The stacked die module contains only inorganic materials, Si, SiO2, Cu and Si3N4 thereby remaining thin with an overall enhanced thermal performance. In this study, thermal simulations were completed for High Bandwidth Memory (HBM) with solder capped micro bumps and compared to direct bond Cu-Cu interconnects using ANSYS ICEPAK. The effect of minimizing the thermal gradient and thermal conductivity on the performance in the stack was analyzed. In order to understand the drivers for the differing results, the effect of die thickness and interconnect design on thermal performance of HBM is also evaluated. Given the boundary conditions of ambient temperature of 450C and an operating power of 2W on each die in both the 4+1 high HBMs with a micro bump or a Cu-Cu interconnect the junction temperature difference were substantial, 9 degrees. The solder capped micro bump stack reached a junction temperature of 670C, while the Cu-Cu stack reached 590C. For an 8 die stack HBM configuration, the direct bond Cu-Cu-stack has a 25% reduction of junction temperature compared to the standard micro bump stack. More importantly, the difference between the junction temperature of hottest and coolest die in the stack is reduced from 330C with micro bumps to 50C for the Cu-Cu. The timing margin requirements and refresh rate would be significantly reduced for the memory cells throughout the die stack in a direct bond in","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"989-998"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82492312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Additive Manufacturing of Magnetic Components for Heterogeneous Integration","authors":"Yi Yan, Lanbing Liu, C. Ding, L. Nguyen, J. Moss, Y. Mei, G. Lu","doi":"10.1109/ECTC.2017.282","DOIUrl":"https://doi.org/10.1109/ECTC.2017.282","url":null,"abstract":"In an effort to simplify the process of integrating magnetic components to power electronics circuits, an additive manufacturing (AM) process, or commonly known as 3D-printing, for fabricating magnetic components is studied in this work. A commercial multi-extruder paste-extrusion 3D printer was evaluated for making magnetic components. We developed two material systems for printing magnetic cores: (1) curable powdered iron paste system, and (2) sinterable ferrite system. We used commercial nanosilver paste for the conductive winding. A half piece of constant-flux inductor (CFI) and a planar inductor were fabricated in this study. For the half piece CFI, 3D-printing was used with nanosilver paste and low-temperature curable powdered iron paste. The printed winding was sintered at 250 deg C for 30 minutes firstly and then magnetic paste was printed to cover the sintered winding. The magnetic paste was cured at 230 deg C for one hour without any external pressure to form the structure. Two printed pieces were connected to form the full size CFI. Inductance of the CFI was measured to be about 3.5 µH. The DC resistance of the winding was 59 m. For the planar inductor, 3D printing was used with nanosilver paste and high-temperature sinterable ferrite paste. It was sintered at 920oC for 14 hours without any external pressure to form the structure. The inductance of the planar inductor was measured to be about 792 nH. The DC resistance of the winding was 15 m. Microstructures of the printed inductors were examined by scanning electron microscopy (SEM). Both the winding and core magnetic properties can be improved by adjusting the feed paste formulations and their flow characteristics and fine-tuning the printer parameters.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"324-330"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81539474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Warpage Tuning Study for Multi-chip Last Fan Out Wafer Level Package","authors":"Hung-Yuan Li, Allen Chen, S. Peng, George Pan, Stephen Chen","doi":"10.1109/ECTC.2017.92","DOIUrl":"https://doi.org/10.1109/ECTC.2017.92","url":null,"abstract":"In recent years, the IoT popularity pushes the package development of 3C products into a more functional and thinner target. For high I/O density and low cost considered package, the promising Fan-out Wafer Level Packaging (FOWLP) provides a solution to match OSAT existing capability, besides, the chip last process in FOWLP can further enhance the total yield by selectable known-good dies (KGDs). However, under processing, the large portion of molding compound induces high warpage to challenge fabrication limitation. The additional leveling process is usually applied to lower the warpage that caused by the mismatch of coefficient of thermal expansion and Young's modulus from carriers, dies, and molding compound. This process results in the increase of package cost and even induce internal damages that affect device reliability. In order to avoid leveling process and improve warpage trend, in this paper, we simulated several models with different design of molding compound and dies, and then developed a multi-chip last FOWLP test vehicle by package dimension of 12x15 mm2 with 8x9 and 4x9 mm2 multiple dies, respectively. The test vehicle performed three redistribution layers (RDLs) including one fine pitch RDL of line width/line spacing 2um/2um, which is also the advantage of multi-chip last FOWLP, and also exhibited ball on trace structure for another low cost option. For the wafer warpage discussion, the results showed that tuning the thickness of molding compound can improve warpage trend, especially in the application of high modulus carrier, which improved wafer warpage within 1mm, for package warpage discussion, the thinner die can lower the warpage of package. Through well warpage controlling, the multi-chip last FOWLP package with ball on trace design was successfully presented in this paper, and also passed the package level reliability of TCB 1000 cycles, HTSL 1000 hrs, and uHAST 96 hrs, and drop test by board level reliability.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"118 1","pages":"1384-1391"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87002580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reflow Warpage Induced Interconnect Gaps between Package/PCB and PoP Top/Bottom Packages","authors":"Kaiqiang Peng, W. Xu, Zhenkai Qin, Lei Feng, L. Lai, W. Koh","doi":"10.1109/ECTC.2017.281","DOIUrl":"https://doi.org/10.1109/ECTC.2017.281","url":null,"abstract":"Package warping during SMT reflow is a seriousconcern as warpage induced interconnect failures suchas Head-in-Pillow (HiP) and Non-Wet-Open (NWO) must be controlled. In this study, the high temperature reflow dynamicwarpage characteristics of BGA packages are examinedusing a simple, controlled gap between the solder balland printed paste interconnect to simulate separation andlifting of the joint due to package warping. By measuringthe in-situ gaps during reflow, the threshold gap valuethat will result in failures is determined. The controlledgap experimental may also be applied to investigatemaximum warpage allowed for the top PoP memorypackage in a PoP stack assembly. The experimental set up and procedures aredescribed in detail. Actual SMT failure results are usedto compare the threshold gap values that suggest failurecould occur. Based on the correlation, it is possible tobacktrack the interconnect gap values to maximumpackage warpage limits as used in industry standards forhigh temperature flatness requirements for BGA packages.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"32 1","pages":"1378-1383"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90292250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Performance Chip-Partitioned Millimeter Wave Passive Devices on Smooth and Fine Pitch InFO RDL","authors":"Che-Wei Hsu, C. Tsai, J. Hsieh, K. Yee, Chuei-Tang Wang, Douglas Yu","doi":"10.1109/ECTC.2017.251","DOIUrl":"https://doi.org/10.1109/ECTC.2017.251","url":null,"abstract":"High performance millimeter wave passive devices are realized on smooth, fine pitch InFO redistribution layer (RDL). These passive devices are balun, power combiner, coupler, and microstrip line and the electrical performances are measured from 0.1GHz to 67 GHz through VNA. The measurement results show that the transmission loss of on-InFO balun (4.3 dB), the power divider (4.3 dB), and the coupler (4.9 dB) outperforms on-chip one by 2.1 dB, 1 dB, and 0.2 dB, respectively. While the transmission loss of microstrip line (0.34 dB/mm) is better than on-chip one by 0.17 dB/mm at 60 GHz. Furthermore, the parasitic of InFO chip-package interconnection has been investigated and compared to other technologies with and without solder bumps. The parasitic resistance, inductance, and capacitance for InFO interconnection are 75 %, 76 %, and 14 % lower than those for chip-last, face-down technology. Parasitic resistance for InFO RDL is 10 % lower than that for chip-first face-down technology with uneven RDL.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"254-259"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90075979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Panel-Based Integrated Passive Device for RF Applicatio","authors":"Ming-Hung Chen, Tzu-Hsing Chiang, Jia-Hao Zhang, Hsu-Chiang Shih, Sheng-Chi Hsieh, T. Lee, C. Hung","doi":"10.1109/ECTC.2017.256","DOIUrl":"https://doi.org/10.1109/ECTC.2017.256","url":null,"abstract":"In this paper, a mass production solution of integrated passive device utilized on radio frequency communication systems was proposed through a glass panel platform where the size could be up to 408 mm * 512 mm and provided 1-layer capacitor and 1-layer inductor for IPD design. The structure characterization of panel-based IPD was performed as well as the electrical stability and RF functional test were evaluated to show the capability reference for further applications. The panel-based process could also provide a cost effective solution on emerging production.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"13 1","pages":"185-189"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85013412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Low-Profile Flow Sensing System for Monitoring of Cerebrospinal Fluid with a New Ventriculoamniotic Shunt","authors":"Yanfei Chen, C. Howe, S. Emery, S. Greene, Puneeth Shridhar, W. Yeo, Y. Chun","doi":"10.1109/ECTC.2017.173","DOIUrl":"https://doi.org/10.1109/ECTC.2017.173","url":null,"abstract":"Fetal hydrocephalus is a condition involvingexcessive accumulation of intraventricular cerebrospinal fluidwith ventricular dilation. It often leads to malformation ordevastating neurological consequences of developing fetalbrains. Recent advances in fetal imaging have triggered thedevelopment of a ventriculoamniotic shunt. However, there arestill concerns about shunt clogging or obstruction with theexisting devices. Here, we introduce a low-profile, ventriculoamniotic shunt device, integrated with a microflowsensor to relieve abnormal high intracranial pressure, whileenabling real-time monitoring of the fluid dynamics. The shuntprototype is manufactured by using a low-profile flexiblecomposite tubing and superelastic nitinol anchors. The flexibleand stretchable microflow sensor is uniquely designed andfabricated by using two metallic nanomembranes encapsulatedby biocompatible silicone elastomer. Flow monitoringperformance of the sensor is demonstrated in vitro using acustom-built flow circulation model with a peristaltic pump. The highly sensitive, microflow sensor measures variousincoming fluid velocity from 0.037 to 0.3 m/s, corresponding tothe capacitance changed from 0.49 pF to 1.43 pF. Collectively, we demonstrate the feasibility of a microflow sensor for directintegration with the ventriculoamniotic shunt device for thetreatment of aqueductal stenosis.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"58 1","pages":"230-235"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84155258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optoelectronic Chip Assembly Process of Optical MCM","authors":"M. Tokunari, Koji Masuda, Hsiang-Han Hsu, T. Hisada, S. Nakagawa, R. Langlois, Patrick Jacques, P. Fortier","doi":"10.1109/ECTC.2017.204","DOIUrl":"https://doi.org/10.1109/ECTC.2017.204","url":null,"abstract":"Assembly process reliability for Optical Multi-Chip Modules (MCM) is studied and improved. In the optoelectronic (OE) chip assembly for the Optical MCM, the OE chip with Au stud bump is joined with Sn-Ag-Cu (SAC) soldered in a through-waveguide via on an organic substrate to obtain high optical coupling efficiency. Since solid-liquid diffusion of Au to molten SAC is rapid, and formation of brittle intermetallic compounds such as AuSn4 is observed by an energy-dispersive X-ray analysis, and as a result the temperature and the dwell time for the chip assembly process should minimized. Furthermore, if OE chips are underfilled, resin could infiltrate into the total internal reflection mirror cavity, and it will not reflect anymore. On the other hand, Au - SAC joints are not mechanically stable without underfill because of a large thermal stress from the coefficient of thermal expansion mismatch between the OE chip and the optical waveguide-integrated organic substrate. The issue is solved by using sidefill encapsulation instead of underfill. Appropriate material selection of a high viscosity and high thixotropic index prevented infiltration under the chip. The effect of the sidefill process is verified by simulation and experimental results. The chip assembly with sidefill passes more than 1500 deep thermal cycles from -55 °C to 125 °C.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"95 1","pages":"545-550"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85889823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}