2017 IEEE 67th Electronic Components and Technology Conference (ECTC)最新文献_第7页

Electrical Performance of High Density 10 µm Diameter 20 µm Pitch Cu-Pillar with Chip to Wafer Assembly 高密度10µm直径20µm间距铜柱与晶圆组装的电气性能

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.38

A. Garnier, L. Arnaud, R. Franiatte, A. Toffoli, S. Moreau, F. Bana, S. Chéramy

{"title":"Electrical Performance of High Density 10 µm Diameter 20 µm Pitch Cu-Pillar with Chip to Wafer Assembly","authors":"A. Garnier, L. Arnaud, R. Franiatte, A. Toffoli, S. Moreau, F. Bana, S. Chéramy","doi":"10.1109/ECTC.2017.38","DOIUrl":"https://doi.org/10.1109/ECTC.2017.38","url":null,"abstract":"Microbump-based interconnects with 20 µm pitch have been fabricated on 300 mm wafers using industrial tools. Good processes control enables to get narrow standard deviations for the microbumps height (0.2 µm) and diameter (0.4 µm). Assembly was studied with chip to wafer (CtW) test vehicles by either mass reflow (MR) or thermo-compression (TC) with or without non-conductive paste (NCP). MR and TC processes result in suitable CtW alignments without significant defects at bonding interface. TC NCP assembly suffers from larger misalignment and underfill entrapment, reducing top to bottom bonding section. Consequently, unit electrical resistance is lower for MR and TC processes with ~25 m ascribed to pure vertical link, than for TC NCP process exhibiting ~50 m vertical link with larger standard deviation (15 m versus 2 m). Intermetallic compounds have been studied and Ni3Sn4 proves to be the main contributor for electrical resistance in our configuration where SnAg is sandwiched between 2 Ni layers. Electrical yield measured on daisy chains is very good (close to or higher than 90%) for MR or TC, even on more than 20,000 interconnects. For TC NCP, electrical yield remains to be improved, particularly on large daisy chains. Finally, an original electrical test has been designed and successfully implemented to characterize top to bottom misalignment. These results are promising for future high performance computing products that would require 20 µm pitch microbumps.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"82 1","pages":"999-1007"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91402536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Glass Based 3D-IPD Integrated RF ASIC in WLCSP WLCSP中基于玻璃的3D-IPD集成射频ASIC

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.328

T. Lee, Yung-shun Chang, Che-Ming Hsu, Sheng-Chi Hsieh, Pao-Nan Lee, Yu-Chang Hsieh, Long-Ching Wang, Lijuan Zhang

引用次数: 12

Infusing Inorganics into the Subsurface of Polymer Redistribution Layer Dielectrics for Improved Adhesion to Metals Interconnects 注入无机物到聚合物重分布层电介质的亚表面以提高与金属互连的附着力

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.277

Shreya Dwarakanath, P. Raj, Collen Z. Leng, V. Smet, M. Losego, V. Sundaram, R. Tummala

引用次数: 4

Co-Design for Low Warpage and High Reliability in Advanced Package with TSV-Free Interposer (TFI) 基于TSV-Free Interposer (TFI)的先进封装低翘曲高可靠性协同设计

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.31

F. Che, M. Kawano, M. Ding, Y. Han, S. Bhattacharya

{"title":"Co-Design for Low Warpage and High Reliability in Advanced Package with TSV-Free Interposer (TFI)","authors":"F. Che, M. Kawano, M. Ding, Y. Han, S. Bhattacharya","doi":"10.1109/ECTC.2017.31","DOIUrl":"https://doi.org/10.1109/ECTC.2017.31","url":null,"abstract":"TSV-Free Interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. Co-design modelling methodology is established for TFI technology with considering wafer process, package assembly and package/board level reliability and thermal performance to optimize structure design, wafer process, assembly process and material selection. Experimental results are used for validating warpage modelling results. Through wafer level modelling, suitable carrier wafer and EMC materials are recommended to control wafer warpage less than 2mm. Effects of package substrate coefficient of thermal expansion (CTE) and stiffener on assembly induced package warpage are simulated to reduce package warpage. The recommended materials and geometry design based on reliability are aligned with that from wafer and package warpage simulation results. The final test vehicle (TV) design and material selection are determined based on co-design modelling results for achieving successful TFI wafer process and package assembly process and long term package/board level reliability.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"21 1","pages":"853-861"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73987271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

New Method to Separate Failure Modes by Transient Thermal Analysis of High Power LEDs 大功率led瞬态热分析分离失效模式的新方法

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.137

A. Hanss, E. Liu, M. Schmid, D. Müller, U. Karbowski, Robert Derix, G. Elger

{"title":"New Method to Separate Failure Modes by Transient Thermal Analysis of High Power LEDs","authors":"A. Hanss, E. Liu, M. Schmid, D. Müller, U. Karbowski, Robert Derix, G. Elger","doi":"10.1109/ECTC.2017.137","DOIUrl":"https://doi.org/10.1109/ECTC.2017.137","url":null,"abstract":"A high reliability of light emitting diode (LED) light sources is essential for general and automotive lighting applications, where exchange of LED components is expensive. Thermal management of modern high power LEDs is crucial for their lifetime. An important aspect is the thermal path for heat conduction. Many different defects can have an influence on this path of an electronic system: on the one hand process failures during production, e.g. voids inside the solder joint, on the other hand typical failures induced by thermo-mechanical stress during their lifetime, like cracks in the solder joint or delamination in the package. The transient thermal analysis (TTA) is a powerful tool to detect changes in the thermal path. Due to improvements in the TTA method during the last years, not only cracks can be detected but also failure modes can be separated, and the root cause can be analyzed by support of transient finite element analysis. In this paper, transient thermal testing is applied and further developed, to monitor the structural integrity of new wafer level LED packages during thermal stress testing. Failure modes are defined and separated. For failure analysis the different defects are simulated by transient finite element analysis and correlated to the TTA results. The simulation results, that solder cracks increase the peak height of the derivative of the transient thermal curves (b(z)). A delamination of an inner layer of the LED package creates additionally to the increase of the peak height also a separation of the b(z) curves between 1 µs and 5 µs. Therefore a transient thermal measurement equipment with a dead time","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"27 1","pages":"1136-1144"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73242413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Novel, High-Throughput, Fiber-to-Chip Assembly Employing Only Off-the-Shelf Components 新颖，高通量，光纤到芯片组装只使用现成的组件

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.185

N. Boyer, Alexander Janta-Polczynski, J. Morissette, S. Martel, Ted W. Lichoulas, S. Kamlapurkar, S. Engelmann, P. Fortier, T. Barwicz

引用次数: 14

Phototriggerable Transient Electronics: Materials and Concepts 光触发瞬态电子学:材料与概念

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.174

O. Phillips, J. Schwartz, A. Engler, Gerald Gourdin, P. Kohl

引用次数: 4

Micro-Hermetic Packaging Technology for Active Implantable Neural Interfaces 主动植入式神经接口的微密封封装技术

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.340

K. Nagarkar, Xiaoxiao Hou, N. Stoffel, E. Davis, Jeffrey M. Ashe, D. Borton

引用次数: 6

Equivalent Thermal Conductivity Model Based Full Scale Numerical Simulation for Thermal Management in Fan-Out Packages 基于等效导热模型的扇出封装热管理全尺寸数值模拟

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.82

Ningyu Wang, Yudan Pi, Wei Wang, Yufeng Jin

{"title":"Equivalent Thermal Conductivity Model Based Full Scale Numerical Simulation for Thermal Management in Fan-Out Packages","authors":"Ningyu Wang, Yudan Pi, Wei Wang, Yufeng Jin","doi":"10.1109/ECTC.2017.82","DOIUrl":"https://doi.org/10.1109/ECTC.2017.82","url":null,"abstract":"Exploring along the road of More Moore with integration degree increasing significantly, different wafer level 3-D technologies are developed facing various circumstances. Thermal issue has become an important concern in IC designing and manufacturing. Fan-out wafer level package (FOWLP), as one of the most popular packaging trends lately, compared to high cost through silicon via (TSV) based 3D integration method, requires system level thermal management. Full scale numerical simulation as a critical procedure is facing huge difficulties, such as huge structure size variation, huge thermal properties variation, in-plane and off-plane displacement, etc. Equivalent thermal conductivity model (ETCM) based full scale numerical simulation for thermal management, which has already been applied to TSV based 3-D ICs with computation consumption significantly decreased, is applied to Fan-out packages in this paper. Equivalent and anisotropic thermal conductivity is calculated and modified concerning FOWLP structure and material thermal properties. A chip-first face-up fan-out package with 100 pads and 100 bumps is modeled and simulated, with mesh elements number drops from 874836 to 174810. With more than 80% computation consumption saved, less than 2% difference in total temperature rise is obtained compared with detail simulation.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"137 1","pages":"2054-2059"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80091122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Thermally Reversible and Crosslinked Polyurethane Based on Diels-Alder Chemistry for Ultrathin Wafer Temporary Bonding at Low-Temperature 基于diols - alder化学的热可逆交联聚氨酯在低温下用于超薄晶片临时键合

2017 IEEE 67th Electronic Components and Technology Conference (ECTC) Pub Date : 2017-05-01 DOI: 10.1109/ECTC.2017.295

Jinhui Li, Qiang Liu, Guoping Zhang, Bin Zhao, R. Sun, C. Wong

引用次数: 3