SACQ Solder Board Level Reliability Evaluation and Life Prediction Model for Wafer Level Packages

Abstract

Wafer Level Chip Scale Packaging (WLCSP) designs, including Wafer Level Fan-Out (WLFO) technologies, are gaining more and more applications for next generation small and thin devices. Since the WLCSP and WLFO packages are mounted directly on the motherboard without a substrate as a buffer, the large coefficient of thermal expansion (CTE) mismatch between the silicon die and the motherboard makes the temperature cycle board level reliability (BLR) of WLCSP and WLFO a tremendous challenge, especially for large body sizes. Currently, a tin (Sn)-silver (Ag)-copper (Cu) solder alloy such as SAC405 is commonly used in WLCSP and WLFO designs, but it has difficulty meeting the board level reliability when the footprint exceeds a certain size. As a result, a new type of solder alloy, SACQ, has been developed in recent years to enhance BLR performance. However, there is little published reliability data of how this new SACQ solder performed in actual package applications. There is also lack of a BLR life prediction model for SACQ solder, unlike the other typical eutectic or leadfree solders. In this paper, the board level temperature cycle reliability of SACQ solder is tested with various WLCSP and WLFO packages configurations. The failure modes associated with SACQ solder are evaluated in detail as well. The temperature cycle performance of SACQ solder is also compared to SAC405 solder, and shows significant improvement consistently over all the packages tested. In addition to the empirical study, a BLR life prediction model for SACQ is also developed based on finite element model (FEM). The required SACQ creep material properties, finite element model setup, damage indicator selection, and life prediction model correlation are all described with details in the paper.