Thermal and Electrical Performance of Direct Bond Interconnect Technology for 2.5D and 3D Integrated Circuits

Currently thermo-compression bonding (TCB) of solder capped micro bumps is the industry standard for high bandwidth memory (HBM) packaging. However, the assembly complexity and high cost has limited its high volume adoption. In addition to assembly challenges, formation of a brittle intermetallic layer reduces electro migration resistance. Furthermore, the underfill between die nearly doubles the stack height and greatly increases thermal resistance of the stacked dies. Currently the layer count stands at four die stacked on a base die. Adding additional layers to the stack poses additional challenges on assembly and ultimately heat dissipation. Direct Bond Interconnect technology is an attractive alternate solution due to the instantaneous bond at room temperature. Two dielectric surfaces are bonded at room temperature, while the metal interconnection (Cu to Cu in most applications) is completed during a subsequent low temperature anneal (1500C – 3000C). The initial dielectric bonding process is performed at ambient temperature and pressure with no adhesive or other filler materials. Bonding takes place instantaneously once the two surfaces are brought into contact. Batch anneal is carried out in a conventional oven. Compared to thermal compression bonding, it has advantages higher throughput and yield which drive the overall bonding costs down. It leverages foundry-standard copper dual-damascene process to achieve scalable, very low cost-of-ownership 3D-interconnect on die. The technology allows Cu-Cu bonding with no additional thickness to the stack. The stacked die module contains only inorganic materials, Si, SiO2, Cu and Si3N4 thereby remaining thin with an overall enhanced thermal performance. In this study, thermal simulations were completed for High Bandwidth Memory (HBM) with solder capped micro bumps and compared to direct bond Cu-Cu interconnects using ANSYS ICEPAK. The effect of minimizing the thermal gradient and thermal conductivity on the performance in the stack was analyzed. In order to understand the drivers for the differing results, the effect of die thickness and interconnect design on thermal performance of HBM is also evaluated. Given the boundary conditions of ambient temperature of 450C and an operating power of 2W on each die in both the 4+1 high HBMs with a micro bump or a Cu-Cu interconnect the junction temperature difference were substantial, 9 degrees. The solder capped micro bump stack reached a junction temperature of 670C, while the Cu-Cu stack reached 590C. For an 8 die stack HBM configuration, the direct bond Cu-Cu-stack has a 25% reduction of junction temperature compared to the standard micro bump stack. More importantly, the difference between the junction temperature of hottest and coolest die in the stack is reduced from 330C with micro bumps to 50C for the Cu-Cu. The timing margin requirements and refresh rate would be significantly reduced for the memory cells throughout the die stack in a direct bond interconnect compared to one built with the traditional micro bump. In addition to the thermal performance, we compared the electrical performance of a conventional micro bump TCB joint to a Cu-Cu interconnect. Specifically, we calculated and compared the S-parameter, resistance (R), inductance (L) and capacitance (C). Through simulation, the effects of assembly misalignment found in manufacturing were evaluated by measuring the corresponding electrical tolerance. A 3D full-wave simulation tool (HFSS) was used to simulate the S-parameters and TDR impedances, while Q3D was used to extract the RLC parameters. Results show that a Cu-Cu interconnect has smaller insertion loss and crosstalk at a higher GHz frequency range than does a conventional TCB joint. The Cu-Cu interconnect also has smaller return loss and impedance variation compared to the TCB joint due to the compact dimension of the interconnect structure. Using an aggressive pattern at 1µm thickness, the Cu-Cu interconnect gave a comparable resistance to a TCB joint. The Cu-Cu interconnect has a smaller inductance than the TCB joint and the parasitic capacitance of the Cu-Cu joint is only 30% of a micro bump joint. Overall, the electrical performance of the Cu-Cu interconnect was better than the solder-capped micro bump. For applications requiring high-speed signaling, the Cu-Cu interconnect would perform better than the conventional mico-bump. In this paper, we share some performance specifications for Cu-Cu interconnect designs relevant for various applications.