Reflow Warpage Induced Interconnect Gaps between Package/PCB and PoP Top/Bottom Packages

Abstract

Package warping during SMT reflow is a seriousconcern as warpage induced interconnect failures suchas Head-in-Pillow (HiP) and Non-Wet-Open (NWO) must be controlled. In this study, the high temperature reflow dynamicwarpage characteristics of BGA packages are examinedusing a simple, controlled gap between the solder balland printed paste interconnect to simulate separation andlifting of the joint due to package warping. By measuringthe in-situ gaps during reflow, the threshold gap valuethat will result in failures is determined. The controlledgap experimental may also be applied to investigatemaximum warpage allowed for the top PoP memorypackage in a PoP stack assembly. The experimental set up and procedures aredescribed in detail. Actual SMT failure results are usedto compare the threshold gap values that suggest failurecould occur. Based on the correlation, it is possible tobacktrack the interconnect gap values to maximumpackage warpage limits as used in industry standards forhigh temperature flatness requirements for BGA packages.