2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第8页

Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated 碳纳米管缺陷免疫数字VLSI:常见问题更新

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105330

Hai Wei, Jie Zhang, Lan Wei, N. Patil, A. Lin, M. Shulaker, Hong-Yu Chen, H. Wong, S. Mitra

引用次数: 10

Property-specific sequential invariant extraction for SAT-based unbounded model checking 用于基于sat的无界模型检查的特定于属性的顺序不变量提取

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105402

Hu-Hsi Yeh, Cheng-Yin Wu, Chung-Yang Huang

引用次数: 1

Low-power multiple-bit upset tolerant memory optimization 低功耗多比特容错存储器优化

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105388

Seokjoong Kim, Matthew R. Guthaus

引用次数: 7

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems 低功耗嵌入式系统中基于STT-RAM存储器的器件架构协同优化

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105369

Cong Xu, Dimin Niu, Xiaochun Zhu, Seung H. Kang, M. Nowak, Yuan Xie

{"title":"Device-architecture co-optimization of STT-RAM based memory for low power embedded systems","authors":"Cong Xu, Dimin Niu, Xiaochun Zhu, Seung H. Kang, M. Nowak, Yuan Xie","doi":"10.1109/ICCAD.2011.6105369","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105369","url":null,"abstract":"Spin-transfer torque random access memory (STT-RAM) is a fast, scalable, durable non-volatile memory which can be embedded into standard CMOS process. A wide range of write speeds from 1ns to 100ns have been reported for STT-RAM. The switching current of magnetic tunnel junction (MTJ) (which is the storage element of STT-RAM) is inversely proportional to the write pulse width. In this work, we propose a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We take the typical in-plane MTJ and advanced perpendicular MTJ (PMTJ) as our optimization targets. Our study shows that reducing write pulse width will harm read latency and energy. It is observed that “sweet spots” of write pulse width which minimize the write energy or write latency of STT-RAM caches may exist. The optimal write pulse width depends on MTJ specifications, STT-RAM capacity and I/O width. The simulation results indicate that by utilizing PMTJ, the optimized STT-RAM can compete against SRAM and DRAM as universal memory replacement in low power embedded systems.1","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"11 1","pages":"463-470"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82029092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39

Improving shared cache behavior of multithreaded object-oriented applications in multicores 改进多核多线程面向对象应用程序的共享缓存行为

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105315

M. Kandemir, Shekhar Srikantaiah, S. Son

{"title":"Improving shared cache behavior of multithreaded object-oriented applications in multicores","authors":"M. Kandemir, Shekhar Srikantaiah, S. Son","doi":"10.1109/ICCAD.2011.6105315","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105315","url":null,"abstract":"Understanding shared cache performance when executing multithreaded object-oriented applications and optimizing these applications for multicores have not received much attention. In this paper, we first quantify the intra-thread and inter-thread cache line (block) reuse characteristics of a set of multithreaded C++ programs when executed in shared cache based multicores. Our results show that, as far as shared on-chip caches are concerned, inter-thread cache line (block) reuse distances are much higher than intra-thread cache line reuse distances. We study the impact of these characteristics on the hit/miss behavior of the shared last-level cache on a commercial multicore machine. We then show that, by rearranging accesses to the objects shared across different threads and to the objects stored in nearby memory locations, inter-thread (temporal and spatial) object reuse distances can be reduced, which in turn helps to reduce inter-thread cache line reuse distances. The results we collected using eight multithreaded applications show that our proposed shared cache-aware code restructuring strategy can reduce misses in the last-level on-chip cache of a commercial multicore machine by 25.4%, on average. These savings in cache misses translate in turn to average execution time improvement of 11.9%.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"118-125"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82182215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimization 通过同时进行浇口尺寸和机械应力优化，改进双Vt工艺

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105410

J. Gu, G. Qu, Lin Yuan, Cheng Zhuo

引用次数: 4

Detecting stability faults in sub-threshold SRAMs 检测亚阈值sram的稳定性故障

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105301

Chen-Wei Lin, Hao-Yu Yang, Chin-Yuan Huang, Hung-Hsin Chen, M. Chao

引用次数: 0

Co-design of channel buffers and crossbar organizations in NoCs architectures noc架构中通道缓冲和跨栏组织的协同设计

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105329

Avinash Karanth Kodi, R. Morris, D. DiTomaso, Ashwini Sarathy, A. Louri

{"title":"Co-design of channel buffers and crossbar organizations in NoCs architectures","authors":"Avinash Karanth Kodi, R. Morris, D. DiTomaso, Ashwini Sarathy, A. Louri","doi":"10.1109/ICCAD.2011.6105329","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105329","url":null,"abstract":"Network-on-Chips (NoCs) have emerged as a scalable solution to the wire delay constraints, thereby providing a high-performance communication fabric for future multicores. Research has shown that power, area and performance of Network-on-Chips (NoCs) architecture are tightly integrated with the design and optimization of the link and router (buffer and crossbar). Recent work has shown that adaptive channel buffers (on-link storage) can considerably reduce power consumption and area overhead by reducing or replacing the power hungry router buffers. However, channel buffer design can lead to Head-of-Line (HoL) blocking which eventually reduces the throughput of the network. In this paper, we explore the design space of organizing channel buffers and router crossbars to improve the performance (latency, throughput) while reducing the power consumption. Our proposed designs analyze the power-performance-area trade-off in designing channel buffers for NoC architectures while overcoming HoL blocking through crossbar optimizations. Our simulation and NoC design synthesis shows that for a 8 × 8 mesh architecture, we can reduce the power consumption by 25–40%, improve performance by 10–25% while occupying 4–13% more area when compared to the baseline architecture.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"43 1","pages":"219-226"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88906869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Post-silicon bug diagnosis with inconsistent executions 后硅错误诊断与不一致的执行

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105414

A. DeOrio, D. Khudia, V. Bertacco

{"title":"Post-silicon bug diagnosis with inconsistent executions","authors":"A. DeOrio, D. Khudia, V. Bertacco","doi":"10.1109/ICCAD.2011.6105414","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105414","url":null,"abstract":"The complexity of modern chips intensifies verification challenges, and an increasing share of this verification effort is shouldered by post-silicon validation. Focusing on the first silicon prototypes, post-silicon validation poses critical new challenges such as intermittent failures, where multiple executions of a same test do not yield a consistent outcome. These are often due to on-chip asynchronous events and electrical effects, leading to extremely time-consuming, if not unachievable, bug diagnosis and debugging processes. In this work, we propose a methodology called BPS (Bug Positioning System) to support the automatic diagnosis of these difficult bugs. During post-silicon validation, lightweight BPS hardware logs a compact encoding of observed signal activity over multiple executions of the same test: some passing, some failing. Leveraging a novel post-analysis algorithm, BPS uses the logged activity to diagnose the bug, identifying the approximate manifestation time and critical design signals. We found experimentally that BPS can localize most bugs down to the exact root signal and within about 1,000 clock cycles of their occurrence.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"159 1","pages":"755-761"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77028935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Optimal layout decomposition for double patterning technology 双图案技术的最优布局分解

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105298

Xiaoping Tang, Minsik Cho

引用次数: 48