2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第9页

PowerRush: A linear simulator for power grid PowerRush:一个用于电网的线性模拟器

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105372

Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou

{"title":"PowerRush: A linear simulator for power grid","authors":"Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou","doi":"10.1109/ICCAD.2011.6105372","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105372","url":null,"abstract":"As the increasing size of power grids, IR drop analysis has become more computationally challenging both in runtime and memory consumption. In this paper, we propose a linear complexity simulator named PowerRush, which consists of an efficient SPICE Parser, a robust circuit Builder and a linear solver. The proposed solver is a pure algebraic method which can provide an optimal convergence without geometric information. It is implemented by Algebraic Multigrid Preconditioned Conjugate Gradient method, in which an aggregation based algebraic multigrid with K-Cycle acceleration is adopted as a preconditioner to improve the robustness of conjugate gradient iterative method. In multigrid scheme, double pairwise aggregation technique is applied to the matrix graph in coarsening procedure to ensure low setup cost and memory requirement. Further, a K-Cycle multigrid scheme is adopted to provide Krylov subspace acceleration at each level to guarantee optimal or near optimal convergence. Experimental results on real power grids have shown that PowerRush has a linear complexity in runtime cost and memory consumption. The DC analysis of a 60 Million nodes power grid can be solved by PowerRush for 0.01mV accuracy in 170 seconds with 21.89GB memory used.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"4 1","pages":"482-487"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84455191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Accelerated statistical simulation via on-demand Hermite spline interpolations 加速统计模拟通过按需埃尔米特样条插值

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105354

R. Kanj, Tong Li, R. Joshi, K. Agarwal, A. Sadigh, David W. Winston, S. Nassif

{"title":"Accelerated statistical simulation via on-demand Hermite spline interpolations","authors":"R. Kanj, Tong Li, R. Joshi, K. Agarwal, A. Sadigh, David W. Winston, S. Nassif","doi":"10.1109/ICCAD.2011.6105354","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105354","url":null,"abstract":"We propose an efficient Hermite spline-based SPICE simulation methodology for accurate statistical yield analysis. Unlike conventional methods, the spline-based transistor tables are built on-demand specific to the transient simulation requirements of the statistical experiments. Compared with traditional MOSFET table models, on-demand spline table models use ∼500X less memory. This makes Hermite spline-based table models practical for use in simulations for process variation modeling. Furthermore, we propose an efficient gate voltage offset approach to model transistor threshold voltage variation. In this scenario, evaluations of the transistor model rely on a single reference table and require one set of spline function evaluations per VT sample point as opposed to two or more sets for VT interpolation. This method is comprehensive and the results are in excellent agreement with traditional BSIM-based simulations. Around 4X improvement in speed, which includes the table generation cost, could be further improved by employing other fast-SPICE techniques or parallelism. To the best of our knowledge, this is the first time such a methodology has been coupled with importance sampling techniques to study the yield of memory designs.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"14 1","pages":"353-360"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81465964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

ATree-based topology synthesis for on-chip network 基于树的片上网络拓扑综合

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105399

J. Cong, Yuhui Huang, Bo Yuan

引用次数: 20

Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuits 混合CMOS/磁性工艺设计套件及其在高性能非易失性逻辑电路设计中的应用

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105334

G. Prenat, B. Dieny, J. Nozieres, G. D. Pendina, K. Torki

引用次数: 6

Post-silicon bug diagnosis with inconsistent executions 后硅错误诊断与不一致的执行

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105414

A. DeOrio, D. Khudia, V. Bertacco

{"title":"Post-silicon bug diagnosis with inconsistent executions","authors":"A. DeOrio, D. Khudia, V. Bertacco","doi":"10.1109/ICCAD.2011.6105414","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105414","url":null,"abstract":"The complexity of modern chips intensifies verification challenges, and an increasing share of this verification effort is shouldered by post-silicon validation. Focusing on the first silicon prototypes, post-silicon validation poses critical new challenges such as intermittent failures, where multiple executions of a same test do not yield a consistent outcome. These are often due to on-chip asynchronous events and electrical effects, leading to extremely time-consuming, if not unachievable, bug diagnosis and debugging processes. In this work, we propose a methodology called BPS (Bug Positioning System) to support the automatic diagnosis of these difficult bugs. During post-silicon validation, lightweight BPS hardware logs a compact encoding of observed signal activity over multiple executions of the same test: some passing, some failing. Leveraging a novel post-analysis algorithm, BPS uses the logged activity to diagnose the bug, identifying the approximate manifestation time and critical design signals. We found experimentally that BPS can localize most bugs down to the exact root signal and within about 1,000 clock cycles of their occurrence.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"159 1","pages":"755-761"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77028935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Optimal layout decomposition for double patterning technology 双图案技术的最优布局分解

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105298

Xiaoping Tang, Minsik Cho

引用次数: 48

Unequal-error-protection codes in SRAMs for mobile multimedia applications 移动多媒体应用中sram中的不等错误保护码

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105300

Xuebei Yang, K. Mohanram

引用次数: 22

Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously 同时利用映射和变形在纳米交叉棒上实现容错逻辑

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105368

Yehua Su, Wenjing Rao

{"title":"Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously","authors":"Yehua Su, Wenjing Rao","doi":"10.1109/ICCAD.2011.6105368","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105368","url":null,"abstract":"Crossbar-based architectures are promising for the future nanoelectronic systems. However, due to the inherent unreliability, defect tolerance schemes are necessary to guarantee the successful implementations of any logic functions. Most of the existing approaches have been based on logic mapping, which exploits the freedom of choosing which variables/products (in a logic function) to map to which of the vertical/horizontal wires (in a crossbar). In this paper, we propose a new defect tolerance approach, namely logic morphing, by exploiting the various equivalent forms of a logic function. This approach explores a new dimension of freedom in achieving defect tolerance, and is compatible with the existing mapping-based approaches. We propose an integrated algorithmic framework, which employs both mapping and morphing simultaneously, and efficiently searches for a successful logic implementation in the combined solution space. Simulation results show that the proposed scheme boosts defect tolerance capability significantly with many-fold yield improvement, while having no extra runtime over the existing approach of performing mapping alone.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"55 1","pages":"456-462"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75948632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Model order reduction of fully parameterized systems by recursive least square optimization 基于递归最小二乘优化的全参数化系统模型降阶

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105380

Zheng Zhang, I. Elfadel, L. Daniel

引用次数: 5

Accelerating aerial image simulation with GPU 利用GPU加速航拍图像仿真

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105323

Hongbo Zhang, Tan Yan, Martin D. F. Wong, Sanjay J. Patel

引用次数: 3