2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第9页

Unequal-error-protection codes in SRAMs for mobile multimedia applications 移动多媒体应用中sram中的不等错误保护码

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105300

Xuebei Yang, K. Mohanram

引用次数: 22

Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously 同时利用映射和变形在纳米交叉棒上实现容错逻辑

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105368

Yehua Su, Wenjing Rao

{"title":"Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously","authors":"Yehua Su, Wenjing Rao","doi":"10.1109/ICCAD.2011.6105368","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105368","url":null,"abstract":"Crossbar-based architectures are promising for the future nanoelectronic systems. However, due to the inherent unreliability, defect tolerance schemes are necessary to guarantee the successful implementations of any logic functions. Most of the existing approaches have been based on logic mapping, which exploits the freedom of choosing which variables/products (in a logic function) to map to which of the vertical/horizontal wires (in a crossbar). In this paper, we propose a new defect tolerance approach, namely logic morphing, by exploiting the various equivalent forms of a logic function. This approach explores a new dimension of freedom in achieving defect tolerance, and is compatible with the existing mapping-based approaches. We propose an integrated algorithmic framework, which employs both mapping and morphing simultaneously, and efficiently searches for a successful logic implementation in the combined solution space. Simulation results show that the proposed scheme boosts defect tolerance capability significantly with many-fold yield improvement, while having no extra runtime over the existing approach of performing mapping alone.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"55 1","pages":"456-462"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75948632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A low-swing crossbar and link generator for low-power networks-on-chip 用于低功耗片上网络的低摆幅横杆和链路发生器

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105418

C. Chen, Sunghyun Park, T. Krishna, L. Peh

{"title":"A low-swing crossbar and link generator for low-power networks-on-chip","authors":"C. Chen, Sunghyun Park, T. Krishna, L. Peh","doi":"10.1109/ICCAD.2011.6105418","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105418","url":null,"abstract":"Networks-on-Chip (NoCs) are emerging as the answer to non-scalable buses for connecting multiple cores in Chip Multi Processors (CMPs), and multiple IP blocks in Multi Processor Systems-on-Chip (MPSoCs). These networks require an extremely low-power datapath to ensure sustained scalability, and higher performance/watt. Crossbars and links form the core of a network datapath, and integrating low-swing links within these will reduce power significantly. Low-swing links however require significant custom circuit design effort to deliver good power efficiency and high bit rate, in the face of noise. As a result, low-swing links have not been able to make it to mainstream chips which rely on crossbar and link generators from RTL. In this paper, we present a datapath generator that creates automated layouts for crossbars with noise-robust low-swing links within them. To the best of our knowledge, this is the first crossbar generator that (1) creates layouts, instead of generating just synthesizable RTL; and (2) integrates noise-robust low-swing links in an automated manner. We demonstrate our generated datapath in a fully-synthesized NoC router, and observe 50% power reduction on datapath.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"31 1","pages":"779-786"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86135498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuits 混合CMOS/磁性工艺设计套件及其在高性能非易失性逻辑电路设计中的应用

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105334

G. Prenat, B. Dieny, J. Nozieres, G. D. Pendina, K. Torki

引用次数: 6

A theoretical probabilistic simulation framework for dynamic power estimation 动态功率估计的理论概率仿真框架

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105407

Lei Wang, M. Olbrich, E. Barke, Thomas Büchner, Markus Bühler, P. Panitz

{"title":"A theoretical probabilistic simulation framework for dynamic power estimation","authors":"Lei Wang, M. Olbrich, E. Barke, Thomas Büchner, Markus Bühler, P. Panitz","doi":"10.1109/ICCAD.2011.6105407","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105407","url":null,"abstract":"As fast non-simulation-based power estimation techniques, probabilistic simulation techniques were widely researched in the 1990s. Spatial and temporal correlations are commonly known as two fundamental challenges of these kinds of techniques. Previous work showed that spatial correlation could be coped with by means of bit-parallel simulation. For temporal correlation that has great impact on estimating glitches, previous work only showed that it could be considered by means of a glitch-filtering scheme which is an approximation algorithm, but did not answer the question whether temporal correlation could be overcome without any approximation. Our work extends conventional probabilistic simulation techniques and puts the essentials and extensions of probabilistic simulation into a theoretical framework. Based on the framework, this paper shows that modeling temporal correlation in probabilistic simulation without any approximation is only possible in theory. Therefore, an improved approximation of the exact method is proposed. Compared to the conventional probabilistic simulation, our prominently improved results prove the effectiveness of our approximation algorithm. At the end of this paper, the advantages and the bottlenecks of probabilistic simulation are concluded in general.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"24 1","pages":"708-715"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90302497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Online clock skew tuning for timing speculation 在线时钟偏差调整时间猜测

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105366

Rong Ye, F. Yuan, Q. Xu

引用次数: 27

Accelerating aerial image simulation with GPU 利用GPU加速航拍图像仿真

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105323

Hongbo Zhang, Tan Yan, Martin D. F. Wong, Sanjay J. Patel

引用次数: 3

Model order reduction of fully parameterized systems by recursive least square optimization 基于递归最小二乘优化的全参数化系统模型降阶

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105380

Zheng Zhang, I. Elfadel, L. Daniel

引用次数: 5

PowerRush: A linear simulator for power grid PowerRush:一个用于电网的线性模拟器

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105372

Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou

{"title":"PowerRush: A linear simulator for power grid","authors":"Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou","doi":"10.1109/ICCAD.2011.6105372","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105372","url":null,"abstract":"As the increasing size of power grids, IR drop analysis has become more computationally challenging both in runtime and memory consumption. In this paper, we propose a linear complexity simulator named PowerRush, which consists of an efficient SPICE Parser, a robust circuit Builder and a linear solver. The proposed solver is a pure algebraic method which can provide an optimal convergence without geometric information. It is implemented by Algebraic Multigrid Preconditioned Conjugate Gradient method, in which an aggregation based algebraic multigrid with K-Cycle acceleration is adopted as a preconditioner to improve the robustness of conjugate gradient iterative method. In multigrid scheme, double pairwise aggregation technique is applied to the matrix graph in coarsening procedure to ensure low setup cost and memory requirement. Further, a K-Cycle multigrid scheme is adopted to provide Krylov subspace acceleration at each level to guarantee optimal or near optimal convergence. Experimental results on real power grids have shown that PowerRush has a linear complexity in runtime cost and memory consumption. The DC analysis of a 60 Million nodes power grid can be solved by PowerRush for 0.01mV accuracy in 170 seconds with 21.89GB memory used.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"4 1","pages":"482-487"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84455191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

ATree-based topology synthesis for on-chip network 基于树的片上网络拓扑综合

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105399

J. Cong, Yuhui Huang, Bo Yuan

引用次数: 20