2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第10页

A low-swing crossbar and link generator for low-power networks-on-chip 用于低功耗片上网络的低摆幅横杆和链路发生器

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105418

C. Chen, Sunghyun Park, T. Krishna, L. Peh

{"title":"A low-swing crossbar and link generator for low-power networks-on-chip","authors":"C. Chen, Sunghyun Park, T. Krishna, L. Peh","doi":"10.1109/ICCAD.2011.6105418","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105418","url":null,"abstract":"Networks-on-Chip (NoCs) are emerging as the answer to non-scalable buses for connecting multiple cores in Chip Multi Processors (CMPs), and multiple IP blocks in Multi Processor Systems-on-Chip (MPSoCs). These networks require an extremely low-power datapath to ensure sustained scalability, and higher performance/watt. Crossbars and links form the core of a network datapath, and integrating low-swing links within these will reduce power significantly. Low-swing links however require significant custom circuit design effort to deliver good power efficiency and high bit rate, in the face of noise. As a result, low-swing links have not been able to make it to mainstream chips which rely on crossbar and link generators from RTL. In this paper, we present a datapath generator that creates automated layouts for crossbars with noise-robust low-swing links within them. To the best of our knowledge, this is the first crossbar generator that (1) creates layouts, instead of generating just synthesizable RTL; and (2) integrates noise-robust low-swing links in an automated manner. We demonstrate our generated datapath in a fully-synthesized NoC router, and observe 50% power reduction on datapath.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"31 1","pages":"779-786"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86135498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

A jumper insertion algorithm under antenna ratio and timing constraints 天线比和时序约束下的跳线插入算法

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105344

X. Gao, L. Macchiarulo

引用次数: 2

Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochips 引脚受限数字微流控生物芯片面向可靠性的广播电极寻址

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105367

Tsung-Wei Huang, Tsung-Yi Ho, K. Chakrabarty

{"title":"Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochips","authors":"Tsung-Wei Huang, Tsung-Yi Ho, K. Chakrabarty","doi":"10.1109/ICCAD.2011.6105367","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105367","url":null,"abstract":"Designs for pin-constrained digital microfluidic biochips (PDMFBs) are receiving much attention because they simplify chip fabrication and packaging, and reduce product cost. To reduce the pin count, broadcast addressing, by minimally grouping electrode sets with non-conflict signal merging, has emerged as a promising solution. Nevertheless, naive signal merging has the potential to cause excessive electrode actuations, which has been reported to have direct and adverse effect on chip reliability. According to recent studies, reliability is an important attribute for PDMFBs particularly developed for medical applications as it directly affects the final medical decision making. However, no research findings have been reported on the reliability problem in pin-constrained designs. To make PDMFBs more feasible for practical applications, we propose in this paper the first matching-based reliability-oriented broadcast-addressing algorithm for PDMFBs. We identify the factors that affect reliability and incorporate into the design-technique attributes that enhance reliability. Experimental results demonstrate the effectiveness of the proposed algorithm.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"4 1","pages":"448-455"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85620104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 47

A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video Coding 多视点视频编码中运动和视差估计的低功耗存储器架构

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105303

B. Zatt, M. Shafique, S. Bampi, J. Henkel

{"title":"A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video Coding","authors":"B. Zatt, M. Shafique, S. Bampi, J. Henkel","doi":"10.1109/ICCAD.2011.6105303","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105303","url":null,"abstract":"A low-power architecture for an on-chip multi-banked video memory for motion and disparity estimation in Multiview Video Coding is proposed. The memory organization (size, banks, sectors, etc.) is driven by an extensive analysis of memory-usage behavior for various 3D-video sequences. Considering a multiple-sleep state model, an application-aware power management scheme is employed to reduce the leakage energy of the on-chip memory. The knowledge of motion and disparity estimation algorithm in conjunction with video properties are considered to predict the memory requirements of each Macroblock. A cost function is evaluated to determine an appropriate sleep mode for the idle memory sectors, while considering the wakeup overhead (latency and energy). The complete motion and disparity estimation architecture is implemented in a 65nm low power IBM technology. The experiments (for various test video sequences) demonstrate that our architecture provides up to 80% leakage energy reduction compared to state-of-the-art. Our scheme processes motion and disparity estimation of four HD1080p views encoding at 30fps with a power consumption of 57mW.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"33 1","pages":"40-47"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86302927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Variation-aware electromigration analysis of power/ground networks 电力/地网络的变化感知电迁移分析

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105387

Di-An Li, M. Marek-Sadowska

引用次数: 17

Structure preserving reduced-order modeling of linear periodic time-varying systems 线性周期时变系统的保结构降阶建模

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105355

Ting Mei, H. Thornquist, E. Keiter, S. Hutchinson

引用次数: 1

The future of clock network synthesis 时钟网络合成的未来

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105339

C. Sze

引用次数: 1

In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation 系统内和动态时钟调优机制，以对抗生命周期性能下降

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105365

Zahra Lak, N. Nicolici

引用次数: 9

CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques caci - p:基于sram的结构的架构级建模，具有先进的减少泄漏技术

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105405

Sheng Li, Ke Chen, Jung Ho Ahn, J. Brockman, N. Jouppi

{"title":"CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques","authors":"Sheng Li, Ke Chen, Jung Ho Ahn, J. Brockman, N. Jouppi","doi":"10.1109/ICCAD.2011.6105405","DOIUrl":"https://doi.org/10.1109/ICCAD.2011.6105405","url":null,"abstract":"This paper introduces CACTI-P, the first architecture-level integrated power, area, and timing modeling framework for SRAM-based structures with advanced leakage power reduction techniques. CACTI-P supports modeling of major leakage power reduction approaches including power-gating, long channel devices, and Hi-k metal gate devices. Because it accounts for implementation overheads, CACTI-P enables in-depth study of architecture-level tradeoffs for advanced leakage power management schemes. We illustrate the potential applicability of CACTI-P in the design and analysis of leakage power reduction techniques of future manycore processors by applying nanosecond scale power-gating to different levels of cache for a 64 core multithreaded architecture at the 22nm technology. Combining results from CACTI-P and a performance simulator, we find that although nanosecond scale power-gating is a powerful way to minimize leakage power for all levels of caches, its severe impacts on processor performance and energy when being used for L1 data caches make nanosecond scale power-gating a better fit for caches closer to main memory.","PeriodicalId":6357,"journal":{"name":"2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"694-701"},"PeriodicalIF":0.0,"publicationDate":"2011-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77242837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 227

Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC 三维集成电路全片通硅孔界面裂纹分析与优化

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2011-11-07 DOI: 10.1109/ICCAD.2011.6105386

Moongon Jung, Xi Liu, S. Sitaraman, D. Pan, S. Lim

引用次数: 43