2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第4页

Semiconductor technologies for smart mobility management 智能移动管理的半导体技术

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.352

Reiner John, M. Schulz, O. Vermesan, K. Kriegel

引用次数: 3

Mutation analysis with coverage discounting 覆盖折扣的突变分析

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.021

Peter Lisherness, Nicole Lesperance, K. Cheng

引用次数: 7

Future memory and interconnect technologies 未来的存储器和互连技术

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.202

Yuan Xie

引用次数: 36

A Critical-Section-Level timing synchronization approach for deterministic multi-core instruction-set simulations 一种用于确定性多核指令集仿真的临界分段级时序同步方法

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.140

Fan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Che-Rung Lee, R. Tsay

引用次数: 5

Machine learning-based anomaly detection for post-silicon bug diagnosis 基于机器学习的后硅bug诊断异常检测

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.5555/2485288.2485411

A. DeOrio, Qingkun Li, M. Burgess, V. Bertacco

引用次数: 42

A multi-level Monte Carlo FPGA accelerator for option pricing in the Heston model 一个多级蒙特卡罗FPGA加速器的期权定价在赫斯顿模型

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.063

C. D. Schryver, P. Torruella, N. Wehn

{"title":"A multi-level Monte Carlo FPGA accelerator for option pricing in the Heston model","authors":"C. D. Schryver, P. Torruella, N. Wehn","doi":"10.7873/DATE.2013.063","DOIUrl":"https://doi.org/10.7873/DATE.2013.063","url":null,"abstract":"The increasing demand for fast and accurate product pricing and risk computation together with high energy costs currently make finance and insurance institutes to rethink their IT infrastructure. Heterogeneous systems including specialized accelerator devices are a promising alternative to current CPU and GPU-clusters towards hardware accelerated computing. It has already been shown in previous work that complex state-of-the-art computations that have to be performed very frequently can be sped up by FPGA accelerators in a highly efficient way in this domain. A very common task is the pricing of credit derivatives, in particular options, under realistic market models. Monte Carlo methods are typically employed for complex or path dependent products. It has been shown that the multi-level Monte Carlo can provide a much better convergence behavior than standard single-level methods. In this work we present the first hardware architecture for pricing European barrier options in the Heston model based on the advanced multi-level Monte Carlo method. The presented architecture uses industry-standard AXI4-Stream flow control, is constructed in a modular way and can be extended to more products easily. We show that it computes around 100 millions of steps in a second with a total power consumption of 3.58 W on a Xilinx Virtex-6 FPGA.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"272 1","pages":"248-253"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73649210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs 快速共享片上存储器架构，用于高效的CGRAs混合计算

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.5555/2485288.2485662

Jongeun Lee, Yeonghun Jeong, Sungsok Seo

{"title":"Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs","authors":"Jongeun Lee, Yeonghun Jeong, Sungsok Seo","doi":"10.5555/2485288.2485662","DOIUrl":"https://doi.org/10.5555/2485288.2485662","url":null,"abstract":"While Coarse-Grained Reconfigurable Architectures (CGRAs) are very efficient at handling regular, compute-intensive loops, their weakness at control-intensive processing and the need for frequent reconfiguration require another processor, for which usually a main processor is used. To minimize the overhead arising in such collaborative execution, we integrate a dedicated sequential processor (SP) with a reconfigurable array (RA), where the crucial problem is how to share the memory between SP and RA while keeping the SP's memory access latency very short. We present a detailed architecture, control, and program example of our approach, focusing on our optimized on-chip shared memory organization between SP and RA. Our preliminary results demonstrate that our optimized memory architecture is very effective in reducing kernel execution times (23.5% compared to a more straightforward alternative), and our approach can reduce the RA control overhead and other sequential code execution time in kernels significantly, resulting in up to 23.1% reduction in kernel execution time, compared to the conventional system using the main processor for sequential code execution.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"44 1","pages":"1575-1578"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84588144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects 考虑工艺变化和弯曲效应的柔性tft模拟电路自动定径技术

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.297

Yen-Lung Chen, Wan-Rong Wu, Guan-Ruei Lu, C. Liu

引用次数: 2

Energy-efficient multicore chip design through cross-layer approach 采用跨层方法设计节能多核芯片

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.156

P. Wettin, Jacob Murray, P. Pande, B. Shirazi, A. Ganguly

引用次数: 22

Qualification and testing process to implement anti-counterfeiting technologies into IC packages 在IC封装中实施防伪技术的鉴定和测试过程

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.237

Nathalie Kae-Nune, Stephanie Pesseguier

{"title":"Qualification and testing process to implement anti-counterfeiting technologies into IC packages","authors":"Nathalie Kae-Nune, Stephanie Pesseguier","doi":"10.7873/DATE.2013.237","DOIUrl":"https://doi.org/10.7873/DATE.2013.237","url":null,"abstract":"Counterfeiting is no longer limited to just fashion or luxury goods, the phenomenon has now reached electronics components which failure represents a high risk to the safety and security of human communities. One way for the semiconductor (SC) industry to fight against counterfeiting of electronic parts is to add technological innovation at the component level itself. The target is to enable the product authentication in a fast and reliable way. Because semiconductor manufacturing is a complex and delicate operation producing highly complex products which are sensitive to many environmental factors, any introduction of changes in its production - which the implementation of anti-counterfeiting (A/C) technologies must also comply to - must undergo thorough testing and qualification steps. This is mandatory to control the compliancy to the strict delivery requirements, quality and reliability level the industry has established, in line with the product performance specifications. This paper aims to explain the comprehensive requirements specification developed by members of semiconductor and related industries in Europe, to add authentication technologies solutions into IC packages. It also describes the qualification processes and testing plans to implement the most adequate and effective anti-counterfeiting technology (A/T). One of the main challenges in this A/C task is to make sure that the added A/C feature in electronic components does not create any additional reliability or failure issue, nor introduce additional risks that will benefit counterfeiters.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"1 1","pages":"1131-1136"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84165304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16