2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第5页

AVICA: An access-time variation insensitive L1 cache architecture AVICA:访问时间变化不敏感的L1缓存架构

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.028

Seokin Hong, Soontae Kim

引用次数: 8

Model predictive control over delay-based differentiated services control networks 基于延迟的差异化服务控制网络模型预测控制

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.234

R. Muradore, D. Quaglia, P. Fiorini

引用次数: 1

Hybrid Prototyping of multicore embedded systems 多核嵌入式系统的混合原型

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.330

Ehsan Saboori, S. Abdi

引用次数: 5

A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot 实时系统的虚拟样机平台，并以两轮机器人为例进行了研究

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.274

Daniel Mueller-Gritschneder, Kun Lu, Erik Wallander, Marc Greim, Ulf Schlichtmann

{"title":"A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot","authors":"Daniel Mueller-Gritschneder, Kun Lu, Erik Wallander, Marc Greim, Ulf Schlichtmann","doi":"10.7873/DATE.2013.274","DOIUrl":"https://doi.org/10.7873/DATE.2013.274","url":null,"abstract":"In today's real-time system design, a virtual prototype can help to increase both the design speed and quality. Developing a virtual prototyping platform requires realistic modeling of the HW system, accurate simulation of the real-time SW, and integration with a reactive real-time environment. Such a VP simulation platform is often difficult to develop. In this paper, we propose a case-study of autonomous two-wheeled robot to show how to develop a virtual prototyping platform rapidly in SystemC/TLM to adequately aid in the design of this instable system with hard real-time constraints. Our approach is an integration of four major model components. Firstly, an accurate physical model of the robot is provided. Secondly, a virtual world is modeled in Java that offers a 3D environment for the robot to move in. Thirdly, the embedded control SW is developed. Finally, the overall HW system is modeled in SystemC at transaction level. This HW model wraps the physical model, interacts with the virtual world, and simulates the real-time SW by integrating an Instruction Set Simulator of the embedded CPU. By integrating these components into a platform, designers can efficiently optimize the embedded SW architecture, explore the design space and check real-time conditions for different system parameters such as buffer sizes, CPU frequency or cache configurations.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"13 1","pages":"1331-1334"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84079726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Probabilistic timing analysis on conventional cache designs 传统高速缓存设计的概率时序分析

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.132

Leonidas Kosmidis, Charlie Curtsinger, E. Quiñones, J. Abella, E. Berger, F. Cazorla

引用次数: 50

Memristor PUFs: A new generation of memory-based Physically Unclonable Functions 忆阻器puf:新一代基于内存的物理不可克隆功能

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.096

Patrick Koeberl, Ünal Koçabas, A. Sadeghi

引用次数: 114

Innovative energy storage solutions for future electromobility in smart cities 面向未来智慧城市电动交通的创新储能解决方案

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.348

K. Green, S. González, Ruud Wijtvliet

引用次数: 9

Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systems 基于片上网络的多处理器系统寿命扩展的可靠性驱动任务映射

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.149

Anup Das, Akash Kumar, B. Veeravalli

{"title":"Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systems","authors":"Anup Das, Akash Kumar, B. Veeravalli","doi":"10.7873/DATE.2013.149","DOIUrl":"https://doi.org/10.7873/DATE.2013.149","url":null,"abstract":"Shrinking transistor geometries, aggressive voltage scaling and higher operating frequencies have negatively impacted the lifetime reliability of embedded multi-core systems. In this paper, a convex optimization-based task-mapping technique is proposed to extend the lifetime of a multiprocessor systems-on-chip (MPSoCs). The proposed technique generates mappings for every application enabled on the platform with variable number of cores. Based on these results, a novel 3D-optimization technique is developed to distribute the cores of an MPSoC among multiple applications enabled simultaneously. Additionally, reliability of the underlying network-on-chip links is also addressed by incorporating aging of links in the objective function. Our formulations are developed for directed acyclic graphs (DAGs) and synchronous dataflow graphs (SDFGs), making our approach applicable for streaming as well as non-streaming applications. Experiments conducted with synthetic and real-life application graphs demonstrate that the proposed approach extends the lifetime of an MPSoC by more than 30% when applications are enabled individually as well as in tandem.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"8 1","pages":"689-694"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83324808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 77

Efficient software-based fault tolerance approach on multicore platforms 多核平台上基于软件的高效容错方法

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.194

Hamid Mushtaq, Z. Al-Ars, K. Bertels

引用次数: 29

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories 利用片上存储器的寄生电容抑制有源功率门控引起的功率/地噪声

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2013-03-18 DOI: 10.7873/DATE.2013.253

Xuan Wang, Jiang Xu, Wei Zhang, Xiaowen Wu, Yaoyao Ye, Zhehui Wang, M. Nikdast, Zhe Wang

{"title":"Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories","authors":"Xuan Wang, Jiang Xu, Wei Zhang, Xiaowen Wu, Yaoyao Ye, Zhehui Wang, M. Nikdast, Zhe Wang","doi":"10.7873/DATE.2013.253","DOIUrl":"https://doi.org/10.7873/DATE.2013.253","url":null,"abstract":"By integrating multiple processing units and memories on a single chip, multiprocessor system-on-chip (MPSoC) can provide higher performance per energy and lower cost per function to applications with growing complexity. In order to maintain the power budget, power gating technique is widely used to reduce the leakage power. However, it will introduce significant power/ground (P/G) noises, and threat the reliability of MPSoCs. With significant area, power and performance overheads, traditional methods rely on reinforced circuits or fixed protection strategies to reduce P/G noises caused by power gating. In this paper, we propose a systematic approach to actively alleviating P/G noises using the parasitic capacitance of on-chip memories through sensor network on-chip (SENoC). We utilize the parasitic capacitance of on-chip memories as dynamic decoupling capacitance to suppress P/G noises and develop a detailed Hspice model for related study. SENoC is developed to not only monitor and report P/G noises but also coordinate processing units and memories to alleviate such transient threats at run time. Extensive evaluations show that compared with traditional methods, our approach saves 11.7% to 62.2% energy consumption and achieves 13.3% to 69.3% performance improvement for different applications and MPSoCs with different scales. We implement the circuit details of our approach and show its low area and energy consumption overheads.","PeriodicalId":6310,"journal":{"name":"2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"12 1","pages":"1221-1224"},"PeriodicalIF":0.0,"publicationDate":"2013-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76343011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4