Energy-efficient multicore chip design through cross-layer approach

P. Wettin, Jacob Murray, P. Pande, B. Shirazi, A. Ganguly
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引用次数: 22

Abstract

Traditional multi-core designs, based on the Network-on-Chip (NoC) paradigm, suffer from high latency and power dissipation as the system size scales up due to the inherent multi-hop nature of communication. Introducing long-range, low power, and high-bandwidth, single-hop links between far apart cores can significantly enhance the performance of NoC fabrics. In this paper, we propose design of a small-world network based NoC architecture with on-chip millimeter (mm)-wave wireless links. The millimeter wave small-world NoC (mSWNoC) is capable of improving the overall latency and energy dissipation characteristics compared to the conventional mesh-based counterpart. The mSWNoC helps in improving the energy dissipation, and hence the thermal profile, even further in presence of network-level dynamic voltage and frequency scaling (DVFS) without incurring any additional latency penalty.
采用跨层方法设计节能多核芯片
基于片上网络(NoC)范式的传统多核设计,由于通信固有的多跳特性,随着系统规模的扩大,会出现高延迟和功耗的问题。在相距较远的核心之间引入远程、低功耗和高带宽的单跳链路可以显著提高NoC结构的性能。在本文中,我们提出了基于片上毫米波无线链路的小世界网络NoC架构的设计。与传统的基于网格的毫米波小世界NoC相比,mSWNoC能够改善整体延迟和能量耗散特性。mSWNoC有助于改善能量耗散,从而进一步改善热分布,甚至在网络级动态电压和频率缩放(DVFS)存在的情况下,也不会产生任何额外的延迟损失。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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