Nano Communication Networks最新文献

{"title":"Design and analysis of a fault tolerance nano-scale code converter based on quantum-dots","authors":"Changgui Xie ,&nbsp;Xin Zhao ,&nbsp;Nima Jafari Navimipour","doi":"10.1016/j.nancom.2024.100530","DOIUrl":"10.1016/j.nancom.2024.100530","url":null,"abstract":"<div><p>Quantum-dot cellular automata (<em>QCA</em>), a nano-scale computer framework, is developing as a potential alternative to current transistor-based technologies. However, it is susceptible to a variety of fabrication-related errors and process variances because it is a novel technology. As a result, QCA-based circuits pose reliability-related problems since they are prone to faults. To address the dependability challenges, it is becoming increasingly necessary to create fault-tolerance QCA-based circuits. On the other hand, the applications of code converters in digital systems are essential for rapid signal processing. Using fault-tolerance <em>XOR</em> and multiplexer, this research suggests a nano-based binary-to-gray and gray-to-binary code converter circuit in a single layer to increase efficiency and reduce complexity. The fault-tolerance performance of the suggested circuits against cell omission, misalignment, displacement, and extra cell deposition faults has significantly improved. Concerning the generalized design metrics of QCA circuits, the fault-tolerance designs have been contrasted with the existing structures. The proposed fault-tolerance circuits' energy dissipation findings have been calculated using the precise <em>QCADesigner-E</em> power estimator tool. Using the QCADesigner-E program, the proposed circuits' functionality has been confirmed. The results implied the high efficiency and applicability of the proposed designs.</p></div>","PeriodicalId":54336,"journal":{"name":"Nano Communication Networks","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142012110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and performance evaluation for electromagnetic micro/nano-gateway","authors":"Akram Galal ,&nbsp;Xavier Hesselbach","doi":"10.1016/j.nancom.2024.100527","DOIUrl":"10.1016/j.nancom.2024.100527","url":null,"abstract":"<div><p>The Internet of nano-things communication has increased attention in recent years, serving different applications in many fields. Such applications need uplink and downlink communication between the nano-network and the macro-domain world through macro/nano-interfaces, where nano-sensors/actuators communicate with smart hybrid devices called micro/nano-gateways. The analytical evaluation of such gateways is mandatory, as it requires a precise study of their performance in handling traffic in the upstream/downstream directions. In this paper, an analytical evaluation of the micro/nano-gateway performance is studied using queueing theory to describe the behavior of the gateway handling the nano-network upstream traffic. The analytical investigation illustrates how different classes of upstream traffic will be processed by the gateway and distributed over three different queues according to traffic characteristics. The study shows the effect of the number of running servers inside each queue and the buffer size on the overall performance of the micro/nano-gateway.</p></div>","PeriodicalId":54336,"journal":{"name":"Nano Communication Networks","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S1878778924000334/pdfft?md5=fa5698b97b62967fefb2f1aeb5bb4282&pid=1-s2.0-S1878778924000334-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141785166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dual banyan network (DBN) design: A quantum-dot cellular automata (QCA) based approach","authors":"Jadav Chandra Das ,&nbsp;Bikash Debnath ,&nbsp;Debashis De ,&nbsp;V. Murali Mohan","doi":"10.1016/j.nancom.2024.100528","DOIUrl":"10.1016/j.nancom.2024.100528","url":null,"abstract":"<div><p>The inputs use a non-blocking internal process to distribute the data using address of the port of the receiver using a non-blocking interior multistage transmission architecture known as a dual banyan network (DBN). The DBN is a primary component in many communication and switching applications because it efficiently routes and switches data packets. This study shows how to construct a single-layer DBN using QCA. A single layer 2 × 2 crossbar network (CBN) with two inputs and two outputs is suggested and developed in QCA to create the proposed communication architecture. In this study, a 2 × 2 CBN is used as a preliminary building block to create a 4 × 4 DBN. We present a detailed analysis of the DBN design, including its architecture, functionality, and performance evaluation. For a fault-free crossbar switch design, the consequence of a fault that affects the control line is noticed and surpassed. Similarly, the proposed architectures' fault tolerance has been described by considering fault scenarios at the 2 × 2 CBN control lines. Considering the logic gates, number of clock cycles, and device size complexity of the designs are measured. All of the designs were implemented using QCADesigner software. The power dissipation of the suggested layouts.</p></div>","PeriodicalId":54336,"journal":{"name":"Nano Communication Networks","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141849683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and simulation of a metamaterial polarization-rotator wall for isolation improvement in SIW fed MIMO DRA for D-band applications","authors":"Emmanuel K. Chemweno,&nbsp;Pradeep Kumar,&nbsp;Thomas J.O. Afullo","doi":"10.1016/j.nancom.2024.100524","DOIUrl":"10.1016/j.nancom.2024.100524","url":null,"abstract":"<div><p>In this research, a metamaterial polarization-rotator (MTMPR) wall is proposed for mutual coupling reduction in a <span><math><mrow><mn>2</mn><mo>×</mo><mn>2</mn></mrow></math></span> multiple-input multiple-output (MIMO) antenna. A substrate integrated waveguide (SIW) based dielectric resonator antenna (DRA) is the preferred topology for the D-band frequency antenna design. The antenna elements are closely packed to achieve high antenna integration. The effect of the proposed isolation technique on the bandwidth performance and radiation characteristics of the antenna is investigated. Simulation results show that the proposed antenna exhibits a −10 dB impedance bandwidth of 19.5% (136.68 GHz–166.28 GHz), a gain of 11.06 dBi and a high efficiency of 84%. The antenna radiates in the broadside direction, with an isolation performance greater than 21.16 dB across the entire bandwidth of operation. Diversity metrics are also evaluated, indicating low correlation between the antenna elements and suitability of the proposed design for MIMO applications.</p></div>","PeriodicalId":54336,"journal":{"name":"Nano Communication Networks","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S1878778924000309/pdfft?md5=71a3ac5d34b11b1f536c1b46c9465733&pid=1-s2.0-S1878778924000309-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141630427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Probability-based mapping approach for an application-aware networks-on-chip architectures","authors":"Deepa Perumal ,&nbsp;Aravindhan Alagarsamy ,&nbsp;Sundarakannan Mahilmaran ,&nbsp;Gian Carlo Cardarilli ,&nbsp;Seok-Bum Ko","doi":"10.1016/j.nancom.2024.100526","DOIUrl":"https://doi.org/10.1016/j.nancom.2024.100526","url":null,"abstract":"<div><p>In a digital and automation era, on-chip multi-core architecture plays a vital role in effective communication in the field of very large-scale integrated circuits (VLSI). In this paper, we propose a unique mapping approach in which a probability-based core selection from the application benchmark into the center to eccentric way of placement of cores in the standard network architecture improves the performance of networks-on-chip (NoC). The proposed approach utilizes a structured mapping strategy, in contrast to the random mapping. This characteristic renders the proposed method a robust solution for a diverse range of NoC architectures irrespective of scale. The proposed approach provides better quality of service (QoS) with optimal total communication bandwidth and average hop count. The performance of the proposed mapping approach is validated with various experiments over standard and real-time benchmarks. The investigation results indicate that the total communication cost over real-time NoC benchmarks for the proposed mapping approach offers 43.06%, 22.75%, and 16.69% average improvement over CastNet, NMAP, and mapGtoM respectively. Furthermore, we adopt uniform geometric and shuffled traffic patterns to identify the latency and throughput of the proposed probability-based mapping approach. The investigation results indicate that the proposed mapping approach outperforms existing mapping procedures.</p></div>","PeriodicalId":54336,"journal":{"name":"Nano Communication Networks","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141606025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quad-functioning Parity Layout for Nanocomputing: A QCA Design","authors":"Angshuman Khan ,&nbsp;Ali Newaz Bahar ,&nbsp;Rajeev Arya","doi":"10.1016/j.nancom.2024.100525","DOIUrl":"https://doi.org/10.1016/j.nancom.2024.100525","url":null,"abstract":"<div><p>Quantum dot cellular automata (QCA) is considered an alternative to conventional technologies like CMOS (Complementary Metal-Oxide-Semiconductor) technology due to its potential for lower power consumption, higher speed, and increased device density. QCA introduces a novel approach to designing nano communication circuits and systems. Nano communications data mistakes are detected via parity generators and checkers. The parity bit of each data block ensures that the number of 1’s is either even or odd. Consequently, the system requires four circuits: an even parity generator, an odd parity generator, an even parity checker, and an odd parity checker. The whole system requires more space and cell complexity. In this work, we propose a QCA architecture that serves as a generator for both even and odd parities, as well as a checker for both even and odd parities. It is a quad-functioning circuit that performs four distinct operations within a single design, utilizing 118 QCA cells and occupying an area of 0.17 μm². The recommended approach uses an efficient XOR gate, resulting in improvements across several performance metrics. QCAPro calculates energy dissipation and design parameters. The recommended QCA circuit outperformed similar QCA circuits in size, complexity, and energy dissipation. The circuit's design cost functions are also low. There has been a 17% reduction in latency and an 86% improvement in QCA-specific costs when compared to the optimal existing design. Moreover, it necessitates a 40% reduction in majority gate usage. The proposed design may compete effectively with other equivalent higher-order circuit designs by reducing the need for multiple blocks in conventional circuits to execute the same task. This architecture holds potential benefits for nano processors and nano communication networks.</p></div>","PeriodicalId":54336,"journal":{"name":"Nano Communication Networks","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141607760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and implementation of a nano-scale high-speed multiplier for signal processing applications","authors":"Seyed-Sajad Ahmadpour ,&nbsp;Nima Jafari Navimipour ,&nbsp;Noor Ul Ain ,&nbsp;Feza Kerestecioglu ,&nbsp;Senay Yalcin ,&nbsp;Danial Bakhshayeshi Avval ,&nbsp;Mehdi Hosseinzadeh","doi":"10.1016/j.nancom.2024.100523","DOIUrl":"10.1016/j.nancom.2024.100523","url":null,"abstract":"<div><p>Digital signal processing (DSP) is an engineering field involved with increasing the precision and dependability of digital communications and mathematical processes, including equalization, modulation, demodulation, compression, and decompression, which can be used to produce a signal of the highest caliber. To execute vital tasks in DSP, an essential electronic circuit such as a multiplier plays an important role, continually performing tasks such as the multiplication of two binary numbers. Multiplier is a crucial component utilized to implement a wide range of DSP tasks, including convolution, Fourier transform, discrete wavelet transforms (DWT), filtering and dithering, multimedia information processing, and more. A multiplier device includes a clock and reset buttons for more flexible operational control. Each digital signal processor constitutes a multiplier unit. A multiplier unit functions entirely autonomously from the central processing unit (CPU); consequently, the CPU is burdened with a significantly reduced amount of work. Since DSP algorithms must constantly carry out multiplication tasks, the employment of a high-speed multiplier to execute fast-speed filtering processes is vital. The previous multipliers had lots of weaknesses, such as high energy, low speed, and high area, because they implemented this necessary circuit based on traditional technology such as complementary metal-oxide semiconductor (CMOS) and very large-scale integration (VLSI). To solve all previous drawbacks in this necessary circuit, we can use nanotechnology, which directly affects the performance of the multiplier and can overcome all previous issues. One of the alternative nanotechnologies that can be used for designing digital circuits is quantum dot cellular automata, which is high speed, low area, and low power. Therefore, this manuscript suggests a quantum technology-based multiplier for DSP applications. In addition, some vital circuits, such as half adder, full adder, and ripple carry adder (RCA), are suggested for designing a multiplier. Moreover, a systolic array, accumulator, and multiply and accumulate (MAC) unit are proposed based on the quantum technology-based multiplier. Nonetheless, each of the suggested frameworks has a coplanar configuration without rotated cells. The suggested structure is developed and verified utilizing the QCADesigner 2.0.3 tools. The findings showed that all circuits have no complicated configuration, including a higher number of quantum cells, latency, and an optimum area.</p></div>","PeriodicalId":54336,"journal":{"name":"Nano Communication Networks","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141588503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Direction of arrival (DOA) estimation using switched beam antenna with butler matrix at mm-wave frequency","authors":"Mohini Narendra Naik ,&nbsp;Hasanali Gulamali Virani","doi":"10.1016/j.nancom.2024.100514","DOIUrl":"10.1016/j.nancom.2024.100514","url":null,"abstract":"<div><p>This paper presents a butler matrix-based microstrip hexagonal patch antenna with a direction of arrival (DOA) estimation approach for mm-wave application. The hexagonal-shaped patch antenna had been designed with a Z-shaped slot with an eight-port butler matrix. The DOA estimation is also done for the switched beam antenna using a novel direction of arrival (DOA) estimation algorithm known as Cramer-Rao lower bound (CRLB). The proposed design leads to significant size reduction and loss minimization. In addition to this, the design had the advantages of being low-cost, lightweight, and small-volume. The entire proposed design provides an operating frequency range of 28 GHz to 39 GHz with a center frequency of 33 GHz. The proposed work makes use of two butler matrices with two 45° phase shifters and 120° phase shifters. The effectiveness of the proposed algorithm and antenna design using the Butler matrix is evaluated for various performance metrics separately. The antenna is designed using Rogers RT/duroid 5880(tm) substrate, and the fabricated prototype is studied. The designed antenna attains high radiation efficiency, and it ranges between 97 and 98 % under both the measures and simulated scenarios under the operating frequency range of 28 GHz to 39 GHz.</p></div>","PeriodicalId":54336,"journal":{"name":"Nano Communication Networks","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141405032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of QCA based memory cell using a novel majority voter with physical validation","authors":"Rupali Singh ,&nbsp;Pankaj Singh ,&nbsp;Ali Nawaz Bahar","doi":"10.1016/j.nancom.2024.100513","DOIUrl":"https://doi.org/10.1016/j.nancom.2024.100513","url":null,"abstract":"<div><p>Quantum Dot Cellular Automata (QCA) is a unique transistor less paradigm which effectively uses change in cell polarization to perform logical operations with high speed, low power and high intricacy. In recent years, the need of high performance memory cell is increased for improving the system performance. This paper presents the design of a QCA based memory cell with read write capabilities. In recent past, most of the QCA circuits are designed using the conventional three input majority voter. The conventional three input majority gate is not fault tolerant. Thus, we need an alternative design which can serve as the majority voter and also shows the fault tolerance. Moreover, the design of three input majority voter is not much addressed . In this paper, an alternative, simple structure of three input majority voter is presented which is better than the conventional one in terms of fault tolerance. In addition to this, the proposed three input majority voter is power aware and efficient to realize various digital circuits. The correctness of the proposed majority voter is validated through the physical proof. Moreover, the proposed gate is subjected to cell displacement defect to investigate the testability. The proposed gate is further used to implement rudimentary elements such as XOR gate, multiplexer and D latch. Finally, the design of Random Access Memory (RAM) cell with read, write, set and reset capabilities is proposed using the presented majority voter. The proposed circuits are further subjected to comprehensive analyses for estimation of cost functions and energy dissipation. The investigation of presented circuits manifests the use of proposed majority voter for next generation computing circuits.</p></div>","PeriodicalId":54336,"journal":{"name":"Nano Communication Networks","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141302810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CHLR: Central high-speed lane routing protocol for intra-body flow-guided nanonetworks in terahertz band communication","authors":"Xin-Wei Yao ,&nbsp;Lang Lin ,&nbsp;Masoud Asghari ,&nbsp;Yiwei Chen ,&nbsp;Md Mehedi Hassan Dorjoy ,&nbsp;Qiang Li","doi":"10.1016/j.nancom.2024.100511","DOIUrl":"10.1016/j.nancom.2024.100511","url":null,"abstract":"<div><p>Intra-body flow-guided nanonetworks are nanonetworks that aim to deploy the Internet of Nanothings (IoNT) into the human cardiovascular system. In these nanonetworks, nano-nodes flow in blood vessels (including arteries and veins) for detecting sensitive biological/physical data. Nano-nodes dispatch data to each other and outside devices via Terahertz (THz) waves. Monitoring of different biomarkers, detection of infectious agents, localization of cancer cells, accurate drug delivery, and other medical applications are all potential applications utilizing such networks. However, the physical limitations of the nano-nodes and the high attenuation of terahertz waves in the blood limit data transmission. Therefore, based on the characteristic of laminar blood flow in blood vessels, we proposed a central high-speed lane routing protocol in Yao et al. (2023), which utilized high-speed nano-nodes in the central layer of the blood flow to form a directional relay chain for other non-centric nano-nodes. In this paper, the proposed protocol is studied in depth, described in detail, and evaluated in the parameters of the hand vein scenario. The proposed protocol works well in new scenarios and proves its efficiency in intra-body communication.</p></div>","PeriodicalId":54336,"journal":{"name":"Nano Communication Networks","volume":null,"pages":null},"PeriodicalIF":2.9,"publicationDate":"2024-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141052267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}