IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献_第9页

Special Topic on Spintronic Devices for Energy-Efficient Computing 用于节能计算的自旋电子器件专题

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2023.3264859

Jian-Ping Wang

引用次数: 0

Review of Magnetic Tunnel Junctions for Stochastic Computing 随机计算中磁隧道结的研究进展

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2022.3227062

Brandon R. Zink, Yang Lv, Jian‐Ping Wang

引用次数: 6

INFORMATION FOR AUTHORS 作者信息

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2023.3263712

引用次数: 0

Binarized Neural Network Accelerator Macro Using Ultralow-Voltage Retention SRAM for Energy Minimum-Point Operation 用于能量最小点操作的超低电压保持SRAM二进制化神经网络加速器宏

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-11-30 DOI: 10.1109/JXCDC.2022.3225744

Yusaku Shiotsu;Satoshi Sugahara

{"title":"Binarized Neural Network Accelerator Macro Using Ultralow-Voltage Retention SRAM for Energy Minimum-Point Operation","authors":"Yusaku Shiotsu;Satoshi Sugahara","doi":"10.1109/JXCDC.2022.3225744","DOIUrl":"10.1109/JXCDC.2022.3225744","url":null,"abstract":"A binarized neural network (BNN) accelerator based on a processing-in-memory (PIM)/ computing-in-memory (CIM) architecture using ultralow-voltage retention static random access memory (ULVR-SRAM) is proposed for the energy minimum-point (EMP) operation. The BNN accelerator (BNA) macro is designed to perform stable inference operations at EMP and substantive power-gating (PG) using ULVR at an ultralow voltage (< EMP), which can be applied to fully connected layers (FCLs) with arbitrary shapes and sizes. The EMP operation of the BNA macro, which is enabled by applying the ULVR-SRAM to the macro, can dramatically improve the energy efficiency (TOPS/W) and significantly enlarge the number of parallelized multiply–accumulate (MAC) operations. In addition, the ULVR mode of the BNA macro, which also benefits from the usage of ULVR-SRAM, is effective at reducing the standby power. The proposed BNA macro can show a high energy efficiency of 65 TOPS/W for FCLs. This BNA macro concept using the ULVR-SRAM can be expanded to convolution layers, where the EMP operation is also expected to enhance the energy efficiency of convolution layers.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"134-144"},"PeriodicalIF":2.4,"publicationDate":"2022-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09966581.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44044898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Valley-Spin Hall Effect-Based Nonvolatile Memory With Exchange-Coupling-Enabled Electrical Isolation of Read and Write Paths 基于谷自旋霍尔效应的具有交换耦合的非易失性存储器实现读写路径的电隔离

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-11-29 DOI: 10.1109/JXCDC.2022.3224832

Karam Cho;Sumeet Kumar Gupta

{"title":"Valley-Spin Hall Effect-Based Nonvolatile Memory With Exchange-Coupling-Enabled Electrical Isolation of Read and Write Paths","authors":"Karam Cho;Sumeet Kumar Gupta","doi":"10.1109/JXCDC.2022.3224832","DOIUrl":"10.1109/JXCDC.2022.3224832","url":null,"abstract":"Valley-spin hall (VSH) effect in monolayer WSe2 has been shown to exhibit highly beneficial features for nonvolatile memory (NVM) design. Key advantages of VSH-based magnetic random access memory (VSH-MRAM) over spin orbit torque (SOT)-MRAM include access transistor-less compact bit-cell and low-power switching of perpendicular magnetic anisotropy (PMA) magnets. Nevertheless, large device resistance in the read path (\u0000<inline-formula> <tex-math>$R_{S}$ </tex-math></inline-formula>\u0000) due to low mobility of WSe2 and Schottky contacts deteriorates sense margin (SM), offsetting the benefits of VSH-MRAM. To address this limitation, we propose another flavor of VSH-MRAM that (while inheriting most of the benefits of VSH-MRAM) achieves lower \u0000<inline-formula> <tex-math>$R_{S}$ </tex-math></inline-formula>\u0000 in the read path by electrically isolating the read and write terminals. This is enabled by coupling VSH with electrically isolated but magnetically coupled PMA magnets via interlayer exchange coupling. Designing the proposed devices using object-oriented micromagnetic framework (OOMMF) simulation, we ensure the robustness of the exchange-coupled PMA system under process variations. To maintain a compact memory footprint, we share the read access transistor across multiple bit-cells. Compared with the existing VSH-MRAMs, our design achieves 39%–42% and 36%–46% reduction in read time and energy, respectively, along with \u0000<inline-formula> <tex-math>$1.1times - 1.3times $ </tex-math></inline-formula>\u0000 larger SM at a comparable area. This comes at the cost of \u0000<inline-formula> <tex-math>$1.7times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$2.0times $ </tex-math></inline-formula>\u0000 increase in write time and energy, respectively. Thus, the proposed design is suitable for applications in which reads are more dominant than writes.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"157-165"},"PeriodicalIF":2.4,"publicationDate":"2022-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/09966380.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46359153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Time-Based Compute-in-Memory for Cryogenic Neural Network With Successive Approximation Register Time-to-Digital Converter 逐次逼近寄存器时间-数字转换器低温神经网络中基于时间的内存计算

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-11-29 DOI: 10.1109/JXCDC.2022.3225243

Dong Suk Kang;Shimeng Yu

引用次数: 1

IMAGIN: Library of IMPLY and MAGIC NOR-Based Approximate Adders for In-Memory Computing IMAGIN:用于内存计算的基于IMPLY和MAGIC NOR的近似加法器库

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-11-14 DOI: 10.1109/JXCDC.2022.3222015

Chandan Kumar Jha;Phrangboklang Lyngton Thangkhiew;Kamalika Datta;Rolf Drechsler

{"title":"IMAGIN: Library of IMPLY and MAGIC NOR-Based Approximate Adders for In-Memory Computing","authors":"Chandan Kumar Jha;Phrangboklang Lyngton Thangkhiew;Kamalika Datta;Rolf Drechsler","doi":"10.1109/JXCDC.2022.3222015","DOIUrl":"10.1109/JXCDC.2022.3222015","url":null,"abstract":"In-memory computing (IMC) has attracted significant interest in recent years as it aims to bridge the memory bottleneck in the Von Neumann architectures. IMC also improves the energy efficiency in these architectures. Another technique that has been explored to reduce the energy consumption is the use of approximate circuits, targeted toward error resilient applications. These applications have addition as one of their most frequently used operations. In literature, CMOS-based approximate adder libraries have been implemented to help designers choose from a variety of designs depending on the output quality requirements. However, the same is not true for memristor-based approximate adders targeted for IMC architectures. Hence, in this work, we developed a framework to generate approximate adder designs with varying output errors for the 8-, 12-, and 16-bit adders. We implemented a state-of-the-art scheduling algorithm to obtain the best mapping of these approximate adder designs for IMC. We performed an exhaustive design space exploration to obtain the pareto-optimal approximate adder designs for various design and error metrics. We then proposed IMAGIN, a library of approximate adders compatible with the memristor-based IMC architecture, which are based on the IMPLY and MAGIC design styles. We also performed mean filtering on the Kodak image dataset using the approximate adders from the IMAGIN library. IMAGIN can help designers select from a wide variety of approximate adders depending on the output quality requirements and serve as benchmarks for future research in this direction. All pareto-optimal designs will be made available at \u0000<uri>https://github.com/agra-uni-bremen/JxCDC2022-imagin-add</uri>\u0000.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"68-76"},"PeriodicalIF":2.4,"publicationDate":"2022-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09950064.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46854745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Stateful Logic Using Phase Change Memory 使用相变存储器的状态逻辑

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-11-04 DOI: 10.1109/JXCDC.2022.3219731

Barak Hoffer;Nicolás Wainstein;Christopher M. Neumann;Eric Pop;Eilam Yalon;Shahar Kvatinsky

{"title":"Stateful Logic Using Phase Change Memory","authors":"Barak Hoffer;Nicolás Wainstein;Christopher M. Neumann;Eric Pop;Eilam Yalon;Shahar Kvatinsky","doi":"10.1109/JXCDC.2022.3219731","DOIUrl":"10.1109/JXCDC.2022.3219731","url":null,"abstract":"Stateful logic is a digital processing-in-memory (PIM) technique that could address von Neumann memory bottleneck challenges while maintaining backward compatibility with standard von Neumann architectures. In stateful logic, memory cells are used to perform the logic operations without reading or moving any data outside the memory array. Stateful logic has been previously demonstrated using several resistive memory types, mostly resistive RAM (RRAM). Here, we present a new method to design stateful logic using a different resistive memory-phase change memory (PCM). We propose and experimentally demonstrate four logic gate types (NOR, IMPLY, OR, NIMP) using commonly used PCM materials. Our stateful logic circuits are different than previously proposed circuits due to the different switching mechanisms and functionality of PCM compared to RRAM. Since the proposed stateful logic forms a functionally complete set, these gates enable the sequential execution of any logic function within the memory, paving the way to PCM-based digital PIM systems.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"77-83"},"PeriodicalIF":2.4,"publicationDate":"2022-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09938984.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43676180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

CRUS: A Hardware-Efficient Algorithm Mitigating Highly Nonlinear Weight Update in CIM Crossbar Arrays for Artificial Neural Networks CRUS：一种硬件有效的人工神经网络CIM交叉条阵列中高度非线性权重更新算法

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-11-04 DOI: 10.1109/JXCDC.2022.3220032

Junmo Lee;Joon Hwang;Youngwoon Cho;Min-Kyu Park;Woo Young Choi;Sangbum Kim;Jong-Ho Lee

{"title":"CRUS: A Hardware-Efficient Algorithm Mitigating Highly Nonlinear Weight Update in CIM Crossbar Arrays for Artificial Neural Networks","authors":"Junmo Lee;Joon Hwang;Youngwoon Cho;Min-Kyu Park;Woo Young Choi;Sangbum Kim;Jong-Ho Lee","doi":"10.1109/JXCDC.2022.3220032","DOIUrl":"10.1109/JXCDC.2022.3220032","url":null,"abstract":"Mitigating the nonlinear weight update of synaptic devices is one of the main challenges in designing compute-in-memory (CIM) crossbar arrays for artificial neural networks (ANNs). While various nonlinearity mitigation schemes have been proposed so far, only a few of them have dealt with high-weight update nonlinearity. This article presents a hardware-efficient on-chip weight update scheme named the conditional reverse update scheme (CRUS), which algorithmically mitigates highly nonlinear weight change in synaptic devices. For hardware efficiency, CRUS is implemented on-chip using low precision (1-bit) and infrequent circuit operations. To utilize algorithmic insights, the impact of the nonlinear weight update on training is investigated. We first introduce a metric called update noise (UN), which quantifies the deviation of the actual weight update in synaptic devices from the expected weight update calculated from the stochastic gradient descent (SGD) algorithm. Based on UN analysis, we aim to reduce AUN, the UN average over the entire training process. The key principle to reducing average UN (AUN) is to conditionally skip long-term depression (LTD) pulses during training. The trends of AUN and accuracy under various LTD skip conditions are investigated to find maximum accuracy conditions. By properly tuning LTD skip conditions, CRUS achieves >90% accuracy on the Modified National Institute of Standards and Technology (MNIST) dataset even under high-weight update nonlinearity. Furthermore, it shows better accuracy than previous nonlinearity mitigation techniques under similar hardware conditions. It also exhibits robustness to cycle-to-cycle variations (CCVs) in conductance updates. The results suggest that CRUS can be an effective solution to relieve the algorithm-hardware tradeoff in CIM crossbar array design.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"145-154"},"PeriodicalIF":2.4,"publicationDate":"2022-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09940271.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42642779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Memristive Devices for Time Domain Compute-in-Memory 内存中时域计算的记忆器件

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-10-25 DOI: 10.1109/JXCDC.2022.3217098

Florian Freye;Jie Lou;Christopher Bengel;Stephan Menzel;Stefan Wiefels;Tobias Gemmeke

{"title":"Memristive Devices for Time Domain Compute-in-Memory","authors":"Florian Freye;Jie Lou;Christopher Bengel;Stephan Menzel;Stefan Wiefels;Tobias Gemmeke","doi":"10.1109/JXCDC.2022.3217098","DOIUrl":"10.1109/JXCDC.2022.3217098","url":null,"abstract":"Analog compute schemes and compute-in-memory (CIM) have emerged in an effort to reduce the increasing power hunger of convolutional neural networks (CNNs), which exceeds the constraints of edge devices. Memristive device types are a relatively new offering with interesting opportunities for unexplored circuit concepts. In this work, the use of memristive devices in cascaded time-domain CIM (TDCIM) is introduced with the primary goal of reducing the size of fully unrolled architectures. The different effects influencing the determinism in memristive devices are outlined together with reliability concerns. Architectures for binary as well as multibit multiply and accumulate (MAC) cells are presented and evaluated. As more involved circuits offer more accurate compute result, a tradeoff between design effort and accuracy comes into the picture. To further evaluate this tradeoff, the impact of variations on overall compute accuracy is discussed. The presented cells reach an energy/OP of 0.23 fJ at a size of \u0000<inline-formula> <tex-math>$1.2~{mu{ }}text{m}^{2}$ </tex-math></inline-formula>\u0000 for binary and 6.04 fJ at \u0000<inline-formula> <tex-math>$3.2~mu text{m}^{2}$ </tex-math></inline-formula>\u0000 for \u0000<inline-formula> <tex-math>$4times 4$ </tex-math></inline-formula>\u0000 bit MAC operations.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"119-127"},"PeriodicalIF":2.4,"publicationDate":"2022-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09930136.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44685222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2