IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献_第8页

Special Topic on Energy-Efficient Compute-in-Memory With Emerging Devices 专题:新兴设备的节能内存计算

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2022.3231764

Jae-Sun Seo

引用次数: 0

RFIC 2023 Call for Papers RFIC 2023征稿

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2022.3218810

引用次数: 0

2022 Index IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Vol. 8 探索性固态计算器件和电路IEEE杂志第8卷

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2023.3268019

引用次数: 0

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information 探索性固态计算器件和电路IEEE杂志出版信息

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2023.3263708

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Special Topic on Spintronic Devices for Energy-Efficient Computing 用于节能计算的自旋电子器件专题

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2023.3264859

Jian-Ping Wang

引用次数: 0

Review of Magnetic Tunnel Junctions for Stochastic Computing 随机计算中磁隧道结的研究进展

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2022.3227062

Brandon R. Zink, Yang Lv, Jian‐Ping Wang

引用次数: 6

INFORMATION FOR AUTHORS 作者信息

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2023.3263712

引用次数: 0

Binarized Neural Network Accelerator Macro Using Ultralow-Voltage Retention SRAM for Energy Minimum-Point Operation 用于能量最小点操作的超低电压保持SRAM二进制化神经网络加速器宏

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-11-30 DOI: 10.1109/JXCDC.2022.3225744

Yusaku Shiotsu;Satoshi Sugahara

{"title":"Binarized Neural Network Accelerator Macro Using Ultralow-Voltage Retention SRAM for Energy Minimum-Point Operation","authors":"Yusaku Shiotsu;Satoshi Sugahara","doi":"10.1109/JXCDC.2022.3225744","DOIUrl":"10.1109/JXCDC.2022.3225744","url":null,"abstract":"A binarized neural network (BNN) accelerator based on a processing-in-memory (PIM)/ computing-in-memory (CIM) architecture using ultralow-voltage retention static random access memory (ULVR-SRAM) is proposed for the energy minimum-point (EMP) operation. The BNN accelerator (BNA) macro is designed to perform stable inference operations at EMP and substantive power-gating (PG) using ULVR at an ultralow voltage (< EMP), which can be applied to fully connected layers (FCLs) with arbitrary shapes and sizes. The EMP operation of the BNA macro, which is enabled by applying the ULVR-SRAM to the macro, can dramatically improve the energy efficiency (TOPS/W) and significantly enlarge the number of parallelized multiply–accumulate (MAC) operations. In addition, the ULVR mode of the BNA macro, which also benefits from the usage of ULVR-SRAM, is effective at reducing the standby power. The proposed BNA macro can show a high energy efficiency of 65 TOPS/W for FCLs. This BNA macro concept using the ULVR-SRAM can be expanded to convolution layers, where the EMP operation is also expected to enhance the energy efficiency of convolution layers.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"134-144"},"PeriodicalIF":2.4,"publicationDate":"2022-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09966581.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44044898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Valley-Spin Hall Effect-Based Nonvolatile Memory With Exchange-Coupling-Enabled Electrical Isolation of Read and Write Paths 基于谷自旋霍尔效应的具有交换耦合的非易失性存储器实现读写路径的电隔离

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-11-29 DOI: 10.1109/JXCDC.2022.3224832

Karam Cho;Sumeet Kumar Gupta

{"title":"Valley-Spin Hall Effect-Based Nonvolatile Memory With Exchange-Coupling-Enabled Electrical Isolation of Read and Write Paths","authors":"Karam Cho;Sumeet Kumar Gupta","doi":"10.1109/JXCDC.2022.3224832","DOIUrl":"10.1109/JXCDC.2022.3224832","url":null,"abstract":"Valley-spin hall (VSH) effect in monolayer WSe2 has been shown to exhibit highly beneficial features for nonvolatile memory (NVM) design. Key advantages of VSH-based magnetic random access memory (VSH-MRAM) over spin orbit torque (SOT)-MRAM include access transistor-less compact bit-cell and low-power switching of perpendicular magnetic anisotropy (PMA) magnets. Nevertheless, large device resistance in the read path (\u0000<inline-formula> <tex-math>$R_{S}$ </tex-math></inline-formula>\u0000) due to low mobility of WSe2 and Schottky contacts deteriorates sense margin (SM), offsetting the benefits of VSH-MRAM. To address this limitation, we propose another flavor of VSH-MRAM that (while inheriting most of the benefits of VSH-MRAM) achieves lower \u0000<inline-formula> <tex-math>$R_{S}$ </tex-math></inline-formula>\u0000 in the read path by electrically isolating the read and write terminals. This is enabled by coupling VSH with electrically isolated but magnetically coupled PMA magnets via interlayer exchange coupling. Designing the proposed devices using object-oriented micromagnetic framework (OOMMF) simulation, we ensure the robustness of the exchange-coupled PMA system under process variations. To maintain a compact memory footprint, we share the read access transistor across multiple bit-cells. Compared with the existing VSH-MRAMs, our design achieves 39%–42% and 36%–46% reduction in read time and energy, respectively, along with \u0000<inline-formula> <tex-math>$1.1times - 1.3times $ </tex-math></inline-formula>\u0000 larger SM at a comparable area. This comes at the cost of \u0000<inline-formula> <tex-math>$1.7times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$2.0times $ </tex-math></inline-formula>\u0000 increase in write time and energy, respectively. Thus, the proposed design is suitable for applications in which reads are more dominant than writes.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"157-165"},"PeriodicalIF":2.4,"publicationDate":"2022-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/09966380.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46359153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Time-Based Compute-in-Memory for Cryogenic Neural Network With Successive Approximation Register Time-to-Digital Converter 逐次逼近寄存器时间-数字转换器低温神经网络中基于时间的内存计算

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-11-29 DOI: 10.1109/JXCDC.2022.3225243

Dong Suk Kang;Shimeng Yu

引用次数: 1