{"title":"2022 Index IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Vol. 8","authors":"","doi":"10.1109/JXCDC.2023.3268019","DOIUrl":"10.1109/JXCDC.2023.3268019","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"212-218"},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/10108913.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44065875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Special Topic on Spintronic Devices for Energy-Efficient Computing","authors":"Jian-Ping Wang","doi":"10.1109/JXCDC.2023.3264859","DOIUrl":"10.1109/JXCDC.2023.3264859","url":null,"abstract":"The traditional scaling trend of semiconductor devices is approaching its limit with the node size in manufacturing already down to 2 nm, with a great guidance from Moore’s law. Heterogenous integration has recently been one of the major driving forces to push the semiconductor technologies further, with a great engineering effort to sum up the power of known and established technologies.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"ii-iii"},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/10102339.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49440758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Review of Magnetic Tunnel Junctions for Stochastic Computing","authors":"Brandon R. Zink, Yang Lv, Jian‐Ping Wang","doi":"10.1109/JXCDC.2022.3227062","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3227062","url":null,"abstract":"Modern computing schemes require large circuit areas and large energy consumption for neuromorphic computing applications, such as recognition, classification, and prediction. This is because these tasks require parallel processing on large datasets. Stochastic computing (SC) is a promising alternative to conventional binary computing schemes due to its low area cost, low processing power, and robustness to noise. However, the large area and energy costs for random number generation with CMOS-based circuits make SC impractical for most hardware implementations. For this reason, beyond-CMOS approaches to random number generation have been investigated in recent years. Spintronics is one of the most promising approaches due to the intrinsic stochasticity of the magnetic tunnel junction (MTJ). In this review article, we provide an overview of the literature published in recent years investigating the tunable, intrinsic stochasticity of MTJs and proposing practical methods for random number generation using spintronic hardware.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"173-184"},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62235055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"INFORMATION FOR AUTHORS","authors":"","doi":"10.1109/JXCDC.2023.3263712","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3263712","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"C3-C3"},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/10102689.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49978849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Binarized Neural Network Accelerator Macro Using Ultralow-Voltage Retention SRAM for Energy Minimum-Point Operation","authors":"Yusaku Shiotsu;Satoshi Sugahara","doi":"10.1109/JXCDC.2022.3225744","DOIUrl":"10.1109/JXCDC.2022.3225744","url":null,"abstract":"A binarized neural network (BNN) accelerator based on a processing-in-memory (PIM)/ computing-in-memory (CIM) architecture using ultralow-voltage retention static random access memory (ULVR-SRAM) is proposed for the energy minimum-point (EMP) operation. The BNN accelerator (BNA) macro is designed to perform stable inference operations at EMP and substantive power-gating (PG) using ULVR at an ultralow voltage (< EMP), which can be applied to fully connected layers (FCLs) with arbitrary shapes and sizes. The EMP operation of the BNA macro, which is enabled by applying the ULVR-SRAM to the macro, can dramatically improve the energy efficiency (TOPS/W) and significantly enlarge the number of parallelized multiply–accumulate (MAC) operations. In addition, the ULVR mode of the BNA macro, which also benefits from the usage of ULVR-SRAM, is effective at reducing the standby power. The proposed BNA macro can show a high energy efficiency of 65 TOPS/W for FCLs. This BNA macro concept using the ULVR-SRAM can be expanded to convolution layers, where the EMP operation is also expected to enhance the energy efficiency of convolution layers.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"134-144"},"PeriodicalIF":2.4,"publicationDate":"2022-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09966581.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44044898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Valley-Spin Hall Effect-Based Nonvolatile Memory With Exchange-Coupling-Enabled Electrical Isolation of Read and Write Paths","authors":"Karam Cho;Sumeet Kumar Gupta","doi":"10.1109/JXCDC.2022.3224832","DOIUrl":"10.1109/JXCDC.2022.3224832","url":null,"abstract":"Valley-spin hall (VSH) effect in monolayer WSe2 has been shown to exhibit highly beneficial features for nonvolatile memory (NVM) design. Key advantages of VSH-based magnetic random access memory (VSH-MRAM) over spin orbit torque (SOT)-MRAM include access transistor-less compact bit-cell and low-power switching of perpendicular magnetic anisotropy (PMA) magnets. Nevertheless, large device resistance in the read path (\u0000<inline-formula> <tex-math>$R_{S}$ </tex-math></inline-formula>\u0000) due to low mobility of WSe2 and Schottky contacts deteriorates sense margin (SM), offsetting the benefits of VSH-MRAM. To address this limitation, we propose another flavor of VSH-MRAM that (while inheriting most of the benefits of VSH-MRAM) achieves lower \u0000<inline-formula> <tex-math>$R_{S}$ </tex-math></inline-formula>\u0000 in the read path by electrically isolating the read and write terminals. This is enabled by coupling VSH with electrically isolated but magnetically coupled PMA magnets via interlayer exchange coupling. Designing the proposed devices using object-oriented micromagnetic framework (OOMMF) simulation, we ensure the robustness of the exchange-coupled PMA system under process variations. To maintain a compact memory footprint, we share the read access transistor across multiple bit-cells. Compared with the existing VSH-MRAMs, our design achieves 39%–42% and 36%–46% reduction in read time and energy, respectively, along with \u0000<inline-formula> <tex-math>$1.1times - 1.3times $ </tex-math></inline-formula>\u0000 larger SM at a comparable area. This comes at the cost of \u0000<inline-formula> <tex-math>$1.7times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$2.0times $ </tex-math></inline-formula>\u0000 increase in write time and energy, respectively. Thus, the proposed design is suitable for applications in which reads are more dominant than writes.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"157-165"},"PeriodicalIF":2.4,"publicationDate":"2022-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/09966380.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46359153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Time-Based Compute-in-Memory for Cryogenic Neural Network With Successive Approximation Register Time-to-Digital Converter","authors":"Dong Suk Kang;Shimeng Yu","doi":"10.1109/JXCDC.2022.3225243","DOIUrl":"10.1109/JXCDC.2022.3225243","url":null,"abstract":"This article explores a compute-in-memory (CIM) paradigm’s new application for cryogenic neural network. Using the 28-nm cryogenic transistor model calibrated at 4 K, the time-based CIM macro comprised of the following: 1) area-efficient unit delay cell design for cryogenic operation and 2) area and power efficient, and a high-resolution achievable successive approximation register (SAR) time-to-digital converter (TDC) is proposed. The benchmark simulation first shows that the proposed macro has better latency than the current-based CIM counterpart. Next, the simulation further shows that it has better scalability for a larger size decoder design and process technology optimization.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"128-133"},"PeriodicalIF":2.4,"publicationDate":"2022-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09966349.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42937846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IMAGIN: Library of IMPLY and MAGIC NOR-Based Approximate Adders for In-Memory Computing","authors":"Chandan Kumar Jha;Phrangboklang Lyngton Thangkhiew;Kamalika Datta;Rolf Drechsler","doi":"10.1109/JXCDC.2022.3222015","DOIUrl":"10.1109/JXCDC.2022.3222015","url":null,"abstract":"In-memory computing (IMC) has attracted significant interest in recent years as it aims to bridge the memory bottleneck in the Von Neumann architectures. IMC also improves the energy efficiency in these architectures. Another technique that has been explored to reduce the energy consumption is the use of approximate circuits, targeted toward error resilient applications. These applications have addition as one of their most frequently used operations. In literature, CMOS-based approximate adder libraries have been implemented to help designers choose from a variety of designs depending on the output quality requirements. However, the same is not true for memristor-based approximate adders targeted for IMC architectures. Hence, in this work, we developed a framework to generate approximate adder designs with varying output errors for the 8-, 12-, and 16-bit adders. We implemented a state-of-the-art scheduling algorithm to obtain the best mapping of these approximate adder designs for IMC. We performed an exhaustive design space exploration to obtain the pareto-optimal approximate adder designs for various design and error metrics. We then proposed IMAGIN, a library of approximate adders compatible with the memristor-based IMC architecture, which are based on the IMPLY and MAGIC design styles. We also performed mean filtering on the Kodak image dataset using the approximate adders from the IMAGIN library. IMAGIN can help designers select from a wide variety of approximate adders depending on the output quality requirements and serve as benchmarks for future research in this direction. All pareto-optimal designs will be made available at \u0000<uri>https://github.com/agra-uni-bremen/JxCDC2022-imagin-add</uri>\u0000.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"68-76"},"PeriodicalIF":2.4,"publicationDate":"2022-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09950064.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46854745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Barak Hoffer;Nicolás Wainstein;Christopher M. Neumann;Eric Pop;Eilam Yalon;Shahar Kvatinsky
{"title":"Stateful Logic Using Phase Change Memory","authors":"Barak Hoffer;Nicolás Wainstein;Christopher M. Neumann;Eric Pop;Eilam Yalon;Shahar Kvatinsky","doi":"10.1109/JXCDC.2022.3219731","DOIUrl":"10.1109/JXCDC.2022.3219731","url":null,"abstract":"Stateful logic is a digital processing-in-memory (PIM) technique that could address von Neumann memory bottleneck challenges while maintaining backward compatibility with standard von Neumann architectures. In stateful logic, memory cells are used to perform the logic operations without reading or moving any data outside the memory array. Stateful logic has been previously demonstrated using several resistive memory types, mostly resistive RAM (RRAM). Here, we present a new method to design stateful logic using a different resistive memory-phase change memory (PCM). We propose and experimentally demonstrate four logic gate types (NOR, IMPLY, OR, NIMP) using commonly used PCM materials. Our stateful logic circuits are different than previously proposed circuits due to the different switching mechanisms and functionality of PCM compared to RRAM. Since the proposed stateful logic forms a functionally complete set, these gates enable the sequential execution of any logic function within the memory, paving the way to PCM-based digital PIM systems.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"77-83"},"PeriodicalIF":2.4,"publicationDate":"2022-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09938984.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43676180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}