IEEE Design & Test of Computers最新文献_第4页

Guest Editors' Introduction to Practical Parallel EDA 客座编辑介绍实用并行EDA

IEEE Design & Test of Computers Pub Date : 2013-06-05 DOI: 10.1109/MDAT.2012.2237138

R. Topaloglu, B. Baas

引用次数: 1

Guest Editors' Introduction: Trusted System-on-Chip with Untrusted Components 客座编辑的介绍:受信任的系统芯片与不受信任的组件

IEEE Design & Test of Computers Pub Date : 2013-06-05 DOI: 10.1109/MDAT.2013.2258093

S. Bhunia, D. Agrawal, L. Nazhandali

引用次数: 1

Let's stop trusting software with our sensitive data 让我们不要再相信软件会泄露我们的敏感数据

IEEE Design & Test of Computers Pub Date : 2013-06-05 DOI: 10.1109/MDAT.2013.2259096

Christopher W. Fletcher, Marten van Dijk, S. Devadas

引用次数: 1

Don't forget test! [design-for-test] 别忘了测试!(针对)

IEEE Design & Test of Computers Pub Date : 2013-06-01 DOI: 10.1109/MDAT.2013.2271570

R. Bennetts

引用次数: 0

A look at our industry's challenges 看看我们行业面临的挑战

IEEE Design & Test of Computers Pub Date : 2013-06-01 DOI: 10.1109/MDAT.2013.2269775

A. Ivanov

{"title":"A look at our industry's challenges","authors":"A. Ivanov","doi":"10.1109/MDAT.2013.2269775","DOIUrl":"https://doi.org/10.1109/MDAT.2013.2269775","url":null,"abstract":"h OUR INDUSTRY FACES a complex myriad of potential problems and challenges across all mediums involving design and test, and the resulting solutions and research methods used to counter experience problems are even more varied and comprehensive. Thus, it makes sense for us at some point to introduce a variety of some of the most current and striking areas of contemporary research and experimentation to our readers. While a narrower focus on selected themes is certainly a top priority for us, the reality is that our industry is varied in the truest sense of the word, and the occasional wide-issue can serve immense benefits in representing this point. This is what we have compiled in this issue; a compendium of recent, highly relevant selections that runs the gamut of problems and solutions in design and test, not only from an interindustry standpoint ranging from Trojans to 3D integration, but also from an international perspective that accounts for studies carried out across the globe. We have provided articles that should give our readers a highly interesting, yet widely informative, background on some of the most prevalent issues facing our global industry today. Indeed, our current market is filled with an ever-increasing need to go faster while maintaining fluid and efficient design; and this is a pursuit that must be highlighted on a cross-industry, global scope, if we are to fully take part in the increasing depth of international communication and collaboration. To start things off, we follow up from our last issue’s focus by providing an examination of Trojan threats due to design vulnerability with ‘‘Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution.’’ A reliance on third-party hardware IP is also highlighted as a cause for concern. A protection solution is proposed to combine predeployment design with postdeployment monitoringVa comprehensive method with high hopes for future defense. Our second entry, ‘‘Exploiting Multiple Mahalanobis Distance Metric to Screen Outliers From Analogue Product Manufacturing Test Responses,’’ provides an in-depth explanation from the University of Twente, The Netherlands, of two problemswith the Mahalanobis Distance classification method, before suggesting a new, more effective method of Multiple Mahalanobis. The conclusions are exemplified by the study of a real-world automobile product. A collaboration from New York University researchers is our third entry called ‘‘ExpeditedCompact Architecture for Average Scan Power Reduction,’’ and proposes an architectural solution to strengthen the reliability of chip under test. This selection poses to minimize scan power hot spots and high heat, while upholding design flow and delivering savings in test power. From here, we travel to researchers from the University of Ferhat Abbes in Algeria for our fourth entry, who present ‘‘An Optical BILBO for On-Line Testing of Embedded Systems,’’ an online optical testing approach to detect immedia","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDAT.2013.2269775","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62451063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Time Is Money 时间就是金钱

IEEE Design & Test of Computers Pub Date : 2013-02-01 DOI: 10.1109/MDT.2012.2228294

G. Smith

引用次数: 1

Towards Making Parallel EDA Serve Practical Applications 使并行EDA服务于实际应用

IEEE Design & Test of Computers Pub Date : 2013-02-01 DOI: 10.1109/MDAT.2013.2251831

A. Ivanov

引用次数: 0

Test Technology TC Newsletter 测试技术委员会通讯

IEEE Design & Test of Computers Pub Date : 2013-01-21 DOI: 10.1109/MDAT.2014.2308364

T. Theocharides

引用次数: 0

Accelerating Emulation and Providing Full Chip Observability and Controllability at Run-Time 加速仿真并在运行时提供全芯片的可观察性和可控性

IEEE Design & Test of Computers Pub Date : 2013-01-01 DOI: 10.1109/MDT.2009.91

I. Mavroidis, Ioannis Mavroidis, I. Papaefstathiou

{"title":"Accelerating Emulation and Providing Full Chip Observability and Controllability at Run-Time","authors":"I. Mavroidis, Ioannis Mavroidis, I. Papaefstathiou","doi":"10.1109/MDT.2009.91","DOIUrl":"https://doi.org/10.1109/MDT.2009.91","url":null,"abstract":"Performing hardware emulation on FPGAs is a significantly faster and more accurate approach for the verification of complex designs than software simulation. Therefore, hardware Simulation Accelerator and Emulator co-processor units are used to offload calculation-intensive tasks from the software simulator. However, the communication overhead between the software simulator and the hardware emulator is becoming a new critical bottleneck. Moreover, in a hardware emulation environment it is impossible to bring outside of the chip a large number of internal signals for verification purposes. Therefore, on-chip observability has become a significant issue. In our work we tackle both aforementioned problems. First, we deploy a novel emulation framework that automatically transforms into synthesizable code certain HDL parts of the testbench, in order to offload them from the software simulator and, more importantly, minimize the aforementioned communication overhead. Next, we extend this architecture by adding multiple fast scan-chain paths in the design in order to provide full circuit observability and controllability on the fly. In this paper, we briefly describe our approach for reducing the communication overhead problem, and present, for the first time, our complete innovative system which offers extensive observability and controllability in complex Design Under Tests (DUTs).","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2009.91","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62466831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Hardware Trojans in Wireless Cryptographic Integrated Circuits 无线加密集成电路中的硬件木马

IEEE Design & Test of Computers Pub Date : 2013-01-01 DOI: 10.1109/MDT.2009.162

Yier Jin, Y. Makris

{"title":"Hardware Trojans in Wireless Cryptographic Integrated Circuits","authors":"Yier Jin, Y. Makris","doi":"10.1109/MDT.2009.162","DOIUrl":"https://doi.org/10.1109/MDT.2009.162","url":null,"abstract":"We study the problem of hardware Trojans in wireless cryptographic integrated circuits, wherein the objective is to leak secret information (i.e. the encryption key) through the wireless channel. Using a mixed-signal system-on-chip, consisting of a DES encryption core and a UWB transmitter, we demonstrate the following three key findings of this study: i) Simple malicious modifications to the digital part of a wireless cryptographic chip suffice to leak information without changing the more sensitive analog part. We demonstrate two hardware Trojan examples, which leak the encryption key by manipulating the transmission amplitude or frequency. ii) Such hardware Trojans do not change the functionality of the digital part or the performances of the analog part and their impact on the wireless transmission parameters can be hidden within the fabrication process variations. Hence, neither traditional manufacturing testing nor recently proposed hardware Trojan detection methods will expose them. iii) For the attacker to be able to discern the leaked information from the legitimate signal, effective hardware Trojans must impose some structure to the transmission parameters. While this structure is not known to the defender, advanced statistical analysis of these parameters (i.e. transmission power), may reveal its existence and, thereby, expose the hardware Trojan.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2009.162","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62465648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15