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ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)最新文献

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Reliability evaluation method of low temperature poly-silicon TFTs using dynamic stress 基于动态应力的低温多晶硅TFTs可靠性评估方法
ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095) Pub Date : 2000-03-13 DOI: 10.1109/ICMTS.2000.844424
Y. Uraoka, T. Hatayama, T. Fuyuki
{"title":"Reliability evaluation method of low temperature poly-silicon TFTs using dynamic stress","authors":"Y. Uraoka, T. Hatayama, T. Fuyuki","doi":"10.1109/ICMTS.2000.844424","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844424","url":null,"abstract":"Evaluation method of reliability of low temperature poly-Si using dynamic stress is proposed. Decrease of mobility and ON current was observed under the dynamic stress. We have found that the degradation depends strongly on falling time and the number of repetition. This degradation is dominated by hot electrons and can be improved by adopting LDD structures.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127276817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new extraction method of retention time from the leakage current in 0.23 /spl mu/m DRAM memory cell 从0.23 /spl mu/m DRAM存储单元漏电流中提取保持时间的新方法
ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095) Pub Date : 2000-03-13 DOI: 10.1109/ICMTS.2000.844414
Choong-Mo Nam, Sung-Kye Park, Sang-Ho Lee, J. Suh, G. Yoon, S. Jang
{"title":"A new extraction method of retention time from the leakage current in 0.23 /spl mu/m DRAM memory cell","authors":"Choong-Mo Nam, Sung-Kye Park, Sang-Ho Lee, J. Suh, G. Yoon, S. Jang","doi":"10.1109/ICMTS.2000.844414","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844414","url":null,"abstract":"The retention time distributions of DRAM memory cell with 0.23 /spl mu/m design rule and STI (Shallow Trench Isolation) have been investigated for several process splits that are designed to increase the retention time. A new extraction method of retention time in memory cell is proposed from the cell leakage current behavior at the general test pattern of memory cell array structure. The 50% bit failure time of memory cell is calculated by the proposed method and compared with the measured retention time. The calculated retention time is very well matched with the measured result in several process conditions of memory cell. Thus, this method can be used for extraction of the retention time of high-density DRAM memory (below 0.23 /spl mu/m) from the cell leakage current.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122340038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fabrication of twin transistors using sidewall masks for evaluating threshold voltage fluctuation 利用侧壁掩模制造双晶体管以评估阈值电压波动
ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095) Pub Date : 2000-03-13 DOI: 10.1109/ICMTS.2000.844401
M. Okuno, T. Aoyama, S. Nakamura, R. Sugino, H. Arimoto
{"title":"Fabrication of twin transistors using sidewall masks for evaluating threshold voltage fluctuation","authors":"M. Okuno, T. Aoyama, S. Nakamura, R. Sugino, H. Arimoto","doi":"10.1109/ICMTS.2000.844401","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844401","url":null,"abstract":"We propose a twin MOSFET fabrication technique to evaluate threshold voltage (Vt) fluctuations. Twin gates have been made using SiN sidewall masks that provide exactly the same gate lengths. From the difference in Vt between the twin transistors, we can evaluate the Vt fluctuation due not to a global variations across a wafer, but due to local variations. The standard deviation of the gate length difference between the twin transistors is smaller than 0.48 nm at a gate length of 95 nm.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127598068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterisation of aluminium passivation for TMAH based anisotropic etching for MEMS applications MEMS中基于TMAH各向异性蚀刻的铝钝化特性研究
ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095) Pub Date : 2000-03-13 DOI: 10.1109/ICMTS.2000.844433
K. Lian, S. Smith, N. Rankin, A. Walton, A. Gundlach, T. Stevenson
{"title":"Characterisation of aluminium passivation for TMAH based anisotropic etching for MEMS applications","authors":"K. Lian, S. Smith, N. Rankin, A. Walton, A. Gundlach, T. Stevenson","doi":"10.1109/ICMTS.2000.844433","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844433","url":null,"abstract":"A cross-bridge linewidth test structure has been used to analyse, both electrically and physically, the effect of a new anisotropic silicon etch composition that has been designed to have an increased selectivity with aluminium. To characterise the effect of the etch on aluminium tracks, electrical measurements have been made to obtain sheet resistance and linewidth. These results are presented in combination with SEM micrographs to evaluate the surface quality of the exposed aluminium.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"34 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116341396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new mobility model for circuit simulation in pocket implanted MOSFET's 一种新的用于口袋植入MOSFET电路仿真的迁移率模型
ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095) Pub Date : 2000-03-13 DOI: 10.1109/ICMTS.2000.844413
P. Klein, F. Schuler
{"title":"A new mobility model for circuit simulation in pocket implanted MOSFET's","authors":"P. Klein, F. Schuler","doi":"10.1109/ICMTS.2000.844413","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844413","url":null,"abstract":"A new analytical, physical-based effective mobility model valid in all regimes of device operation from weak to strong inversion together with an extraction method and corresponding test structures is introduced. The model accounts for the influence of the electrical field as well as for the lateral non-uniform doping profile in pocket implanted MOSFET's. Measurements show that the high local channel doping in the pocket implanted regions makes the mobility degradation due to Coulomb scattering with ionized dopants no longer negligible especially for low gate bias voltage thus for low voltage circuit design.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"370 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122772498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Extraction of the channel thermal noise in MOSFETs mosfet中通道热噪声的提取
ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095) Pub Date : 2000-03-13 DOI: 10.1109/ICMTS.2000.844403
Chih-Hung Chen, M. Deen, M. Matloubian, Yuhua Cheng
{"title":"Extraction of the channel thermal noise in MOSFETs","authors":"Chih-Hung Chen, M. Deen, M. Matloubian, Yuhua Cheng","doi":"10.1109/ICMTS.2000.844403","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844403","url":null,"abstract":"An extraction method to obtain the channel thermal noise in MOSFETs directly from DC, scattering parameter and RF noise measurements is presented. In this extraction method, the transconductance (g/sub m/), output resistance (R/sub DS/), and source and drain resistances (R/sub S/ and R/sub D/) are obtained from DC measurements. The gate resistance (R/sub G/) is extracted from scattering-parameter measurements, and the equivalent noise resistance (R/sub n/) is obtained from RF noise measurements. This method has been verified by using the measured data of a 0.36 /spl mu/m n-type MOSFET up to 18 GHz.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130489757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Electromigration test structure designed to identify via failure modes 设计了电迁移测试结构，用于识别通过的失效模式
ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095) Pub Date : 2000-03-13 DOI: 10.1109/ICMTS.2000.844423
T. Sriram
{"title":"Electromigration test structure designed to identify via failure modes","authors":"T. Sriram","doi":"10.1109/ICMTS.2000.844423","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844423","url":null,"abstract":"A new type of electromigration test structure has been demonstrated, which allows detailed understanding of the electromigration behavior of inter-level vias. It is designed to test each via interface independently. It also allows easy failure analysis by constraining the failure location. An example of its application is provided, where a change in the via process led to improved electromigration behavior. The use of this test structure allowed the identification of physical mechanisms for the improved electromigration behavior.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"90 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126026475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
New method for parameter extraction in deep submicrometer MOSFETs 深亚微米mosfet参数提取的新方法
ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095) Pub Date : 2000-03-13 DOI: 10.1109/ICMTS.2000.844428
C. Mourrain, B. Crețu, G. Ghibaudo, P. Cottin
{"title":"New method for parameter extraction in deep submicrometer MOSFETs","authors":"C. Mourrain, B. Crețu, G. Ghibaudo, P. Cottin","doi":"10.1109/ICMTS.2000.844428","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844428","url":null,"abstract":"A new method for the MOSFET parameter extraction including second order mobility attenuation is proposed. The advantage of the method is to remain compatible with previously existing ones avoiding second order derivative procedure and therefore to be applicable for in line parametric test extraction in the microelectronics industry.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126041619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Optimization of low-k dielectric (fluorinated SiO/sub 2/) process and evaluation of yield impact by using BEOL test structures 低k介电介质(氟化SiO/sub 2/)工艺优化及BEOL试验结构对成品率影响的评价
ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095) Pub Date : 2000-03-13 DOI: 10.1109/ICMTS.2000.844432
S. Hsieh, K. Doong, Yens Ho, Sheng-che Lin, Binson Shen, Sing-Mo Tseng, Yeu-Haw Yang, Calvin Hsu
{"title":"Optimization of low-k dielectric (fluorinated SiO/sub 2/) process and evaluation of yield impact by using BEOL test structures","authors":"S. Hsieh, K. Doong, Yens Ho, Sheng-che Lin, Binson Shen, Sing-Mo Tseng, Yeu-Haw Yang, Calvin Hsu","doi":"10.1109/ICMTS.2000.844432","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844432","url":null,"abstract":"This work describes the optimization of low-k dielectric process and evaluation of yield impact by using back end of line (BEOL) test structures. Three splits of the low-k dielectric process were compared with high-density-plasma un-doped-silicon-glass (HDP-USG) process and are electrically characterized with the test structures of the BEOL unit process and integration process parameter extraction. The interconnect capacitance is used as the optimization criteria of low-k dielectric process and the yield impact is reviewed for the concern of manufacturing.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129084097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Extraction of effective LDMOSFET channel length and its application to the modeling LDMOSFET有效沟道长度的提取及其在建模中的应用
ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095) Pub Date : 2000-03-13 DOI: 10.1109/ICMTS.2000.844409
K. Tsuji, K. Terada, M. Minami, K. Tanaka
{"title":"Extraction of effective LDMOSFET channel length and its application to the modeling","authors":"K. Tsuji, K. Terada, M. Minami, K. Tanaka","doi":"10.1109/ICMTS.2000.844409","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844409","url":null,"abstract":"The effective channel length of LD (lateral double diffused) MOSFET is accurately extracted and is applied to develop its circuit simulation model, which has the physical meaning of the channel length and so on. This model is consisted of a simple MOSFET, gate-voltage dependent resistor and three resistors. It is confirmed that the errors between the measured electrical characteristics and the calculated ones are less than 5 percent.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127692491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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