2011 IEEE Workshop on Microelectronics and Electron Devices最新文献

Invited talk: Promises and challenges in light-emitting diodes for lighting applications 特邀演讲:照明应用中发光二极管的前景和挑战

2011 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2011-04-22 DOI: 10.1109/WMED.2011.5767269

E. Schubert

{"title":"Invited talk: Promises and challenges in light-emitting diodes for lighting applications","authors":"E. Schubert","doi":"10.1109/WMED.2011.5767269","DOIUrl":"https://doi.org/10.1109/WMED.2011.5767269","url":null,"abstract":"Lighting technologies based on semiconductor light-emitting diodes (LEDs) offer unprecedented promises that include three major benefits: (i) Gigantic energy savings enabled by efficient conversion of electrical energy to optical energy; (ii) Substantial positive contributions to sustainability through reduced emissions of global-warming gases, acid-rain gases, and toxic substances such as mercury; and (iii) The creation of new paradigms in lighting driven by the unique controllability of solid-state lighting sources. Due to the powerful nature of these benefits, the transition from conventional lighting sources to solid-state lighting is virtually assured. This presentation will illustrate the new world of lighting including the pervasive changes to be expected in lighting, displays, communications, and biotechnology. The presentation will also address the formidable challenges that must be addressed to further advance solid-state lighting technology. These challenges offer opportunities for research and innovation. Specific challenges include light management and carrier transport. As an example, we will discuss new optical thin-film materials with a tunable refractive index. We will also discuss the hotly debated efficiency droop, that is, the decreasing LED efficiency at high currents.","PeriodicalId":443024,"journal":{"name":"2011 IEEE Workshop on Microelectronics and Electron Devices","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126707707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A non-volatile memory array based on nano-ionic Conductive Bridge Memristors 一种基于纳米离子导电桥式忆阻器的非易失性存储阵列

2011 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2011-04-22 DOI: 10.1109/WMED.2011.5767279

S. Wald, Jake Baker, M. Mitkova, N. Rafla

{"title":"A non-volatile memory array based on nano-ionic Conductive Bridge Memristors","authors":"S. Wald, Jake Baker, M. Mitkova, N. Rafla","doi":"10.1109/WMED.2011.5767279","DOIUrl":"https://doi.org/10.1109/WMED.2011.5767279","url":null,"abstract":"Much excitement has been generated over the potential uses of chalcogenide glasses and other materials in circuits as “memristors” or as non-volatile memories. The memristor is a fourth passive two terminal electronic device, postulated by Leon Chua in 1971 and rediscovered in 2008. Our Conductive Bridge Memristor (CBM) changes its resistance in response to current passing through it by building up or dissolving a conductive molecular bridge in an otherwise insulating chalcogenide film. This paper outlines the design and simulation of a non-volatile memory using an array of CBM devices integrated with CMOS access transistors and read/write access circuitry. We have designed and simulated a large memory array layout using CBM devices accessed by an NMOS transistor and CMOS row/column read and write drivers. The design uses a folded-cascode op-amp configured to integrate current on the column as a strategy for sensing the device resistance. Each CBM device is connected to the array through a single minimum size NMOS transistor. The design has been simulated using a SPICE model for the PMC (Programmable Metallization Cell) [7]. We demonstrate the feasibility of accessing the device for read without exceeding the write threshold, and discuss the tradeoff of speed vs. array size associated with this technique. Plans are being developed to fabricate the design on a MOSIS multi project wafer with BEOL processing for the CBM devices.","PeriodicalId":443024,"journal":{"name":"2011 IEEE Workshop on Microelectronics and Electron Devices","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117202860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Adjustable supply voltages and refresh cycle for process variations and temperature changing adaptation in DRAM to minimize power consumption 可调电源电压和刷新周期的过程变化和温度变化适应DRAM，以尽量减少功耗

2011 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2011-04-22 DOI: 10.1109/WMED.2011.5767277

L. Tran, F. Kurdahi, A. Eltawil

引用次数: 1

All digital duty-cycle correction circuit design and its applications in high-performance DRAM 全数字占空比校正电路设计及其在高性能DRAM中的应用

2011 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2011-04-22 DOI: 10.1109/WMED.2011.5767278

Feng Lin

引用次数: 2

Invited tutorial: Energy efficient multi-Gb/s I/O: Circuit and system design techniques 特邀讲座:节能多gb /s I/O:电路与系统设计技术

2011 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2011-04-22 DOI: 10.1109/WMED.2011.5767268

B. Casper

{"title":"Invited tutorial: Energy efficient multi-Gb/s I/O: Circuit and system design techniques","authors":"B. Casper","doi":"10.1109/WMED.2011.5767268","DOIUrl":"https://doi.org/10.1109/WMED.2011.5767268","url":null,"abstract":"Chip-to-chip I/O data rates continue to scale aggressively to keep up with demands brought on by multi-core CPU-based computer and networking systems. Due to increasing bandwidth needs and declining system power budgets, dramatically improving I/O energy efficiency is crucial and is the major challenge currently facing the computer and networking industry. A multi-pronged approach to I/O power reduction will be presented, employing both circuit and interconnect optimization. The use of system level modeling and optimization to co-design the packaging, board interconnect, channel, transmitter, receiver, and clocking will be advocated with examples that demonstrate minimum-power I/O systems. I/O energy reduction depends on both active power minimization as well as the use of aggressive power management methods. Techniques and corresponding examples will be shown that demonstrate I/O power management including dynamic voltage and frequency scaling, low-power standby, and fast wake-up times. This session will provide insight into the challenges and opportunities associated with each low-power technique, using case studies to illustrate state-of-the-art low-power I/O systems.","PeriodicalId":443024,"journal":{"name":"2011 IEEE Workshop on Microelectronics and Electron Devices","volume":"195 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113991051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Invited tutorial: Advanced CMOS transistor technology: Past, present and future 特邀讲座:先进的CMOS晶体管技术:过去，现在和未来

2011 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2011-04-22 DOI: 10.1109/WMED.2011.5767289

S. Datta

{"title":"Invited tutorial: Advanced CMOS transistor technology: Past, present and future","authors":"S. Datta","doi":"10.1109/WMED.2011.5767289","DOIUrl":"https://doi.org/10.1109/WMED.2011.5767289","url":null,"abstract":"Almost half a century later, Gordon Moore's accurate observation that the number of transistors in an integrated circuit doubles every two years continues to be the guiding principle of the semiconductor industry. We have almost taken for granted the apparent corollary; as transistor count increases, each transistor becomes smaller, faster and cheaper. Today, the transistor physical gate length in production is less than 30 nanometer; further brute-force geometric scaling of conventional silicon devices limit faces many fundamental challenges — rising energy consumption, power density and worsening device to device fluctuation being some of the foremost barriers. In this tutorial, I will present the amazing journey of the logic transistor in the last ten years starting with strained channel CMOS transistors, the high-k/metal-gate silicon CMOS transistors and the multiple-gate transistor architecture. Then, I will review the recent breakthroughs in non-silicon (compound semiconductor and germanium) based quantum-well transistor research that are promising transistor architecture for the next decade. I will also describe our research efforts in a new genre of “green” transistors that work on the quantum-mechanical band to band tunneling principle called Tunnel transistors and can operate with the record low energy delay product. Finally, interaction of emerging devices with the circuit and system architecture will also be discussed. This talk will summarize the twenty-first century logic transistor innovations that have and will continue to enhance the energy efficiency and performance of information processing systems through materials, device physics and architectural innovations.","PeriodicalId":443024,"journal":{"name":"2011 IEEE Workshop on Microelectronics and Electron Devices","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121077224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Finite element modeling of a back grinding process for Through Silicon Vias 硅通孔反磨过程的有限元建模

2011 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2011-04-22 DOI: 10.1109/WMED.2011.5767273

A. Abdelnaby, G. Potirniche, F. Barlow, A. Elshabini, R. Parker

引用次数: 2

High-performance transistor evaluation for low-cost embedded DRAM 低成本嵌入式DRAM的高性能晶体管评估

2011 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2011-04-22 DOI: 10.1109/WMED.2011.5767275

Hajime Furusawa, S. Nogami, Takahisa Ogawa, Masanobu Kumazaki, Naoki Okada, H. Yamamoto

引用次数: 0

VT statistics on nanoscale NAND Flash arrays 纳米级NAND闪存阵列的VT统计

2011 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2011-04-22 DOI: 10.1109/WMED.2011.5767274

A. Spessot, A. Calderoni, P. Fantini

引用次数: 0

Invited talk: Label-free biosensing with silicon nanowires 特邀演讲:用硅纳米线进行无标签生物传感

2011 IEEE Workshop on Microelectronics and Electron Devices Pub Date : 2011-04-22 DOI: 10.1109/WMED.2011.5767270

E. Stern, Aleksander Vacic, Nitin K. Rajan, D. Routenberg, J. Criscione, Jason Park, Monika Weber, T. Fahmy, M. Reed

{"title":"Invited talk: Label-free biosensing with silicon nanowires","authors":"E. Stern, Aleksander Vacic, Nitin K. Rajan, D. Routenberg, J. Criscione, Jason Park, Monika Weber, T. Fahmy, M. Reed","doi":"10.1109/WMED.2011.5767270","DOIUrl":"https://doi.org/10.1109/WMED.2011.5767270","url":null,"abstract":"Nanoscale electronic devices have the potential to achieve exquisite sensitivity as sensors for the direct detection of molecular interactions, thereby decreasing diagnostics costs and enabling previously impossible sensing in disparate field environments. Semiconducting nanowire-field effect transistors (NW-FETs) hold particular promise, though contemporary NW approaches are inadequate for realistic applications. We present here a number of top-down fabricated nanowire approaches [1] that are compatible with complementary metal-oxide-semiconductor (CMOS) technology that has not only achieved unprecedented sensitivity, but simultaneously facilitates system-scale integration of nanosensors. These approaches enable a wide range of label-free biochemical and macromolecule sensing applications, such as specific protein and complementary DNA recognition assays, and specific macromolecule interactions at <femtomolar concentrations. We will also discuss the physics of FET sensing, and device-related limits of potential detection [2]. A critical limitation of nanowire sensors is the Debye screening issue [3] which has to date prevented their use in clinical applications and physiologically relevant solutions. We will present an approach that solves this longstanding problem, and demonstrate the detection at clinically important concentrations of biomarkers from whole blood samples [4]. [1] Nature, 445, 519 (2007) [2] Elect. Dev. Lett. 31, 615 (2010) [3] Nano Lett. 7, 3405 (2007) [4] Nature Nanotech. 5, 138 (2010)","PeriodicalId":443024,"journal":{"name":"2011 IEEE Workshop on Microelectronics and Electron Devices","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121768915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0