{"title":"纳米级NAND闪存阵列的VT统计","authors":"A. Spessot, A. Calderoni, P. Fantini","doi":"10.1109/WMED.2011.5767274","DOIUrl":null,"url":null,"abstract":"This paper presents a compact model allowing the investigation of the variability effects in nanoscale NAND Flash arrays. The proposed model describes the NAND string current in the readout conditions, including parasitic capacitive couplings among neighboring cells, and also the cell programming and erase operations. Changing the model parameters to account for their physical fluctuation in a Monte Carlo fashion, the impact of each variability source on the statistical dispersion of the cell threshold-voltage is obtained for state-of-the-art and next generation technology nodes. Good agreement between simulations and experimental results and the low computational load make the proposed methodology a valid solution for the assessment of variability constraints on NAND technology design.","PeriodicalId":443024,"journal":{"name":"2011 IEEE Workshop on Microelectronics and Electron Devices","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"VT statistics on nanoscale NAND Flash arrays\",\"authors\":\"A. Spessot, A. Calderoni, P. Fantini\",\"doi\":\"10.1109/WMED.2011.5767274\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a compact model allowing the investigation of the variability effects in nanoscale NAND Flash arrays. The proposed model describes the NAND string current in the readout conditions, including parasitic capacitive couplings among neighboring cells, and also the cell programming and erase operations. Changing the model parameters to account for their physical fluctuation in a Monte Carlo fashion, the impact of each variability source on the statistical dispersion of the cell threshold-voltage is obtained for state-of-the-art and next generation technology nodes. Good agreement between simulations and experimental results and the low computational load make the proposed methodology a valid solution for the assessment of variability constraints on NAND technology design.\",\"PeriodicalId\":443024,\"journal\":{\"name\":\"2011 IEEE Workshop on Microelectronics and Electron Devices\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE Workshop on Microelectronics and Electron Devices\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WMED.2011.5767274\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE Workshop on Microelectronics and Electron Devices","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WMED.2011.5767274","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a compact model allowing the investigation of the variability effects in nanoscale NAND Flash arrays. The proposed model describes the NAND string current in the readout conditions, including parasitic capacitive couplings among neighboring cells, and also the cell programming and erase operations. Changing the model parameters to account for their physical fluctuation in a Monte Carlo fashion, the impact of each variability source on the statistical dispersion of the cell threshold-voltage is obtained for state-of-the-art and next generation technology nodes. Good agreement between simulations and experimental results and the low computational load make the proposed methodology a valid solution for the assessment of variability constraints on NAND technology design.