Invited tutorial: Energy efficient multi-Gb/s I/O: Circuit and system design techniques

Chip-to-chip I/O data rates continue to scale aggressively to keep up with demands brought on by multi-core CPU-based computer and networking systems. Due to increasing bandwidth needs and declining system power budgets, dramatically improving I/O energy efficiency is crucial and is the major challenge currently facing the computer and networking industry. A multi-pronged approach to I/O power reduction will be presented, employing both circuit and interconnect optimization. The use of system level modeling and optimization to co-design the packaging, board interconnect, channel, transmitter, receiver, and clocking will be advocated with examples that demonstrate minimum-power I/O systems. I/O energy reduction depends on both active power minimization as well as the use of aggressive power management methods. Techniques and corresponding examples will be shown that demonstrate I/O power management including dynamic voltage and frequency scaling, low-power standby, and fast wake-up times. This session will provide insight into the challenges and opportunities associated with each low-power technique, using case studies to illustrate state-of-the-art low-power I/O systems.