All digital duty-cycle correction circuit design and its applications in high-performance DRAM

Abstract

Duty-cycle distortion (DCD) becomes a pressing concern as the data rate in high-performance DRAM interfaces exceeds multi-gigahertz range. In order to preserve or even improve the clock duty cycle on-die across process, voltage, and temperature (PVT) corners, a duty-cycle correction (DCC) circuit is generally desired. This paper investigates a variety of DCC circuits based on different implementations. Two applications using DCC circuits are presented in detail: 1) a digital DCC for high-speed data capture, and 2) an all-digital DCC for production DDR3 DRAMs. Pros and cons for the different approaches are compared based on the simulated and silicon data.